Start execution at address 0

A project log for PDP - Processor Design Principles

Distilling my experience and wisdom about the architecture, organisation and design choices of my CPUs

Yann Guidon / YGDESYann Guidon / YGDES 02/15/2018 at 01:530 Comments

Several processors start execution at more or less arbitrary addresses. There is actually a large variety of approaches and implementations. This was mostly driven in the early (golden age of) microprocessors by the need to have separate RAM and ROM address ranges. Some had a "fast page mode" that favors the first 256 bytes of memory so it was impossible to put ROM at the lower addresses.

The Intel 8088/8086 would boot to FFFFEh (mapped to BIOS EPROM) and locate the IRQ table at 00000h (in DRAM). But the reset vector is also sometimes one entry in the "interrupt vector table" (see the 6809). Should it be in ROM or RAM ? If it's in ROM, you can boot but you can't modify or reallocate the vectors to user code. See the last log Interrupt vector table

Anyway, many current processors boot from a serial EEPROM. Some circuits load the contents of the EEPROM into main RAM or in the cache, so the problem of the overlap of RAM and ROM is now a thing of the past.

Booting at address 0 is easy and future-safe (just look at the x86 and the extension of its address space...)