Update (Nov 2018) - New memory map and decoding - now have 128K RAM and 64K ROM
I'll copy the notes from my schematic by way of an explanation..
Make better use of
- 64k EPROM and 128K SRAM
- Current memory map: ROM=C000-FFFF, RAM=0000-AFFF,IO=B000-BFFF
- Ability to switch ROM out for RAM (top 16K of memory map)
- Any write to ROM should select RAM, enabling write to RAM without switching
- Ability to select which 16K of ROM is addressable by 6502
- Ability to select which 32K of RAM is addressable by 6502
- Ability to have a continuous top 32K of RAM (currently B000-BFFF is memory mapped IO
This is solved through 3 solution approaches as follows..
Move IO access from B000 to 0400 (4 pages, 1KB block)
- Makes normal RAM accessible from 0000 to 01ff and 0800 to C000
- When ROM switched out, 0800 to FFFF contiguous area
- 74HCT138 decoder using A15..A10 as inputs
- /Y0 output is low if IO memory addressed, else high
- Output is connected to current 74HCT138 IO device selector
- Output is connected to RAM CE (if not IO then assume RAM)
- IO select is A15..A11 = 0, A10=1
- When ROM disable is selected, any access to memory is directed to RAM
- When ROM is selected but a write is occurring, direct to RAM
- IO select section is always addressable (0400-07ff)
- Add ROM disable (/DIS) as 6522 port B bit 5, active low (pull up this line as default)
- Include /DIS in ROM and R/W in ROM select logic
- ROM is selected if A15=1, A14=1, /DIS=1 and R/W=1 else it is RAM (unless IO selected)
- Map in RAM only if selecting upper 32K - select 1 of 4 32K banks
- Map in ROM only if selecting upper 16K - select 1 of 4 16K banks
- Add ROM bank select X1,X0 as 6522 port B bit 7,6 (pull up lines as default)
- Add RAM bank select Y1,Y0 as 6522 port B bit 5,4 (pull up lines as default)
- ROM addressing: If A15,A14=1 then ROM A15=PB7,ROM A14=PB6 else ROM A15,A14=1
- RAM addressing: If A15=1 then RAM A16=PB5,RAM A15=PB4 else RAM A16,A15=1
Update (June 2018) - Clock speed doubled - now running @ 5.36Mhz
The clock circuit of my project used a 21.7727Mhz master crystal, which is fed through a 4 bit counter to output the right clock speed for various devices:
- 10.7Mhz for the TM9918
- 2.68Mhz for the 6502 and peripheral chips (6522, 6551)
- 1.34Mhz for the AY-38-8910 and BBC Keyboard matrix hardware strobe
I also have a 5.36Mhz clock available, but in previous attempts at trying this, I end up with a blank screen an/or frozen machine. This led me to believe that my RAM was not fast enough to keep up with the demand at 5.36Mhz.
So I tried swapping out the 70ns RAM chip with a very fast 15ns RAM chip. I also made some software adjustments, mainly putting in extra NOP instructions to delay the speed at which the TMS9918 was being driven and the BBC keyboard was being strobed. To cut a long story short, it turns out that the 15ns chip is glitchy, but the 70ns chip works fine once the software reflects the faster CPU cycles.
I also got a huge amount of insight from the expert folks over at the 6502 forum - turns out my assumptions on the activities of the 6502 across one clock cycle are incorrect, but still my current design does work without any issues - but it's not optimal and I will sort this out in due course.
So I'm mega pleased. I would never have dreamt of a 5.36Mhz 6502 back in the early 80s. The BBC Micro was the fastest 6502 micro around running at 2Mhz, followed by the Atari 8 bits at 1.79Mhz. My machine is more than 2.5 times faster clocked than the BBC, and with the tokenising BASIC interpreter I built (dflat), a serious amount of power is available to write interesting programs :-)... Read more »