The crazy behavior of the Sum gate's power draw is officially solved. By building up the circuit piece by piece and keeping my eye on the current draw continually, I was able to narrow the problem down quite a bit. It only occurred with the inputs in particular positions, and only when power was first applied to the circuit. This sounded an awful lot like latchup so I figured I must be applying too much current to one or more input pins. Playing around with resistor positions and values didn't solve the problem, but with some [insert preferred search engine here]ing around I ran across a great little document here from Analog Devices. It is entitled "Winning the Battle Against Latchup in CMOS Analog Switches" and it clued me in to another way you can get latchup.

As we all know, one should not exceed any of the absolute maximum values listed in a devices datasheet. As far as I could tell, I was not exceeding any maximums, but I hadn't taken time or relative maximums into account. Some values in the datasheet are dependent on others, and the one tripping me up was the maximum allowable voltage on an analog input. The highest voltage on an input is equal to the supply voltage. But on initial power up, which one gets power first? In my case, apparently it was the analog input, thus making that voltage higher than the supply voltage which hadn't quite gotten up to speed yet. Therefor I was exceeding maximums and the device latched up causing a low impedance connection between the input and the power rail. Voila!

The solution? This is covered quite nicely in the document as well and consists of nothing more than placing a schottky diode in line with the power pin of the analog switch. I don't quite follow why this works (magic probably) but it does the trick.

Along the way I also tweaked a lot of resistor values to bring the overall current draw to between 14 and 18 mA depending on what the two inputs are set to. I want to fiddle around with this a bit more to see if I can reduce that further and then I will post a revised schematic.