Log Entries

This is a list of the different modules and sub-modules used in this project so far.

Comparator.asc - buffered comparator

This is a standard comparator made out of a long-tailed differential amplifier followed by an buffer/inverter.

Uses 0c 4r 0d 2npn 3pnp

NAND2.asc - Two input NAND gate made with DTL

A standard implementation of a DTL (Diode-Transistor Logic) NAND gate. I'm using two level shifter diodes to improve the noise margin as well as a (optional) pulldown to VEE that improves the transistor turn-off time a bit whenever necessary.

Uses 0c 3r 4d 1npn 0pnp

NAND3.asc - Three input NAND gate made with DTL

Exactly the same design as the NAND2.asc except one additional input diode.

Uses 0c 3r 5d 1npn 0pnp

D-LATCH.asc - A transparent D-latch of four nand gates.

This is a simple implementation of a regular transparent D-latch. Being transparent means that the clock input is level sensitive and not edge triggered, so the data output will follow the input as long as the clock is high.

It is implemented by four 2-input NAND gates.

Uses 0c 12r 16d 4npn 0pnp

UARTfaker.asc - Fake an incoming serial character

LTSpice doesn't have any provisions for making arbitrary digital stimuli pulse trains, so I just added up a bunch of voltage sources each with a timed pulse to make up a digital pulse train simulating an incoming serial transmission of a single character.

UART-Rx-Sequencer.asc - Generates timing pulses

This generates the timing pulses positioned in the middle of each bit slot of the incoming serial data. It's implemented with a constant current generator charging a capacitor to get a linear ramp. Then an array of eight comparators compares the ramp voltage agains eight different voltages generated by a resistor ladder. The comparators output a falling edge at each bit slot.

Uses 1c 42r 0d 16npn 26pnp (including the submodules)

UART-RX.asc - The main module for UART Reception

Here all submodules are put together with some glue logic to perform the decoding of an incoming serial (RS232) character and output it as 8 bits in parallel.

The startbit of the serial data resets and triggers the timing generator in the Sequencer. Then whenever the sequencer determines that the middle of a data timeslot has been reached it lowers the corresponding output which is connected to the CLK input of one of the eight output latches.

The serial data is also connected to the DATA-input of all latches, so when the CLK goes low on one of them the current data value will be locked.

This repeats eight times and then the sequencer is stopped by the 8th bit resetting a the start/stop flipflop that originally started the process.

Since the latches are transparent their outputs will mimic the serial data stream until they have been locked one-by-one.