I've shared the board design over at OSHPark. Some details not obvious from the schematic:

• The power supply path from the input all the way to the supply pin of the OCXO is 32 mils wide, which is extra width because that's the highest current path in the whole project. The rest of the 3.3V+ supply rails are 16 mils wide.
• A bunch of the bypass caps are lumped together in the schematic near the regulator. Whenever you see that in a schematic you should understand that they're not physically located near each other. Rather, they're scattered around near Vcc pins of ICs for decoupling.
• Not shown on the schematic is that the clock output lines from the fan-out buffer have "meanders" in them to try and make the traces the same physical length. It's unlikely that this will actually matter at 10 MHz (or even 20), or with a stability of only 20 ppb, but it doesn't cost anything to do.

I'm probably going to order the first set of boards today, but I want to make sure the D/A chips fit in the layout before I commit. They're the last untested footprint. I'm also probably going to try and breadboard one and feed it with a basic sawtooth sketch (a tight loop that writes a continuously incrementing value to the D/A) to test it.

The OSHPark shared board used to be linked here, but that board isn't going to work - the 3.3V regulator will overheat badly. I'll link to the final board once it's tested (in about a week and a half).