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FE-5680A ?

A project log for GPS Disciplined xCXO

A DIY GPS disciplined 10 MHz reference clock

nick-sayerNick Sayer 04/20/2016 at 05:282 Comments

I decided to sit down and design a GPS discipline add-on board for the FE-5680A rubidium frequency standard.

The FE-5680A is widely available on eBay and it's Allan Deviation starts at, or perhaps slightly higher than the OH300 (see this page for one experimenter's results), but at taus above 2-3 seconds, it does much better. By the time you get to tau 300 seconds, the ADEV is under 10E-12, where the GPS discipline should result in a very similar downward slope continuing after that.

The design starts with the 15 volt buck converter that's part of the FE-5680A breakout board I sell on Tindie. It's based on the LM3485 and it is designed to take 16-24 VDC @ 25-30W (which should be easily obtainable from a surplus laptop power supply) in and drop it down to 15 VDC at up to 2 amps. An MC34063 converter generates up to 200 mA of 5 volts from some of the 15 volt output.

The +15 and +5 volt supply rails are fed into an edge-mounted DB-9F connector that will mate with the FE-5680A. The +5 rail splits off to power the rest of the circuitry as well.

Most of the rest of the circuit is copied from the GPSDO design that I've already got. However, instead of a DAC, there's a MAX232 TTL to RS-232 level converter that allows the ATTiny841's USART2 pins to connect to the serial I/O of the oscillator. It's that serial interface that will allow the controller to trim the output frequency of the oscillator. In place of the DAC's !CS line, the controller is fed the oscillator's !READY output signal. This allows the controller to wait until the oscillator is ready before discipline begins. Also, since the output of the oscillator is a sine wave rather than a square wave, a self-biased inverter with a DC blocking cap i used to convert it into a TTL square wave, before it heads off to the clock buffer chip and the rest of the circuitry.

Because the 2nd USART of the ATTiny841 is shared with the ISP pins, we need to take a couple of precautions to insure that programming the chip works and doesn't have any unpleasant side effects. For the transmit pin (to the oscillator), we use an AND gate with !RESET to pass the serial data to the MAX232. When !RESET is held low for programming, the serial out pin will also be held low (idle should be high rather than low, but that's still better than passing the programming data through to the oscillator). For the receive pin (from the oscillator), we only need to add a 10kΩ series resistor to give the programmer priority over that pin of the controller.

This board should wind up costing about US$75 (not including the oscillator). The expectation is that the Allan deviation should start at around 2E-11 @ tau 1s and head downwards at some constant slope from there. Long term time deviation should rise up to an asymptote at ±10 ns by the action of the GPS discipline.

I've uploaded a preliminary schematic to the Files section of the project. Discuss!

Discussions

Yann Guidon / YGDES wrote 04/20/2016 at 06:48 point

I'm waiting for a fe-5680b to arrive... I've seen that there are MANY variations of this reference so you can't be sure that any 5680 will work...

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Nick Sayer wrote 04/20/2016 at 07:06 point

That's true, but the most common one is what this project is geared for - one with a 10 MHz sine output on the DB9 itself, with trimming via RS-232.

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