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A project log for GPS Disciplined xCXO

A DIY GPS disciplined 10 MHz reference clock

nick-sayerNick Sayer 04/28/2016 at 01:140 Comments

One of the things that had to be done for the FE-5680A variant is to protect the oscillator's serial input from the ISP signals while the controller is being programmed. This is necessary because the USART1 pins are shared with the ISP pins for programming. For the transmit pin from the oscillator, a simple series resistor is enough to allow the programmer to override it during programming, but for the output pin, it's not quite that simple. My solution for the prototype was a simple AND gate with the TX pin and !RESET. When reset is high - when programming is not taking place - the TX pin flows through to the RS-232 level converter and then the oscillator. But when !RESET is low, the output will stay low and the data on the TX pin will be blocked.

That sort of works, but the idle condition for a serial line is high, not low. Holding the line low instead should be harmless, but it's not perfect. It's conceivable that this might elicit some kind of bug in the oscillator's controller (hopefully not).

What would be better would be this truth table:

MISO/TXD!RESETOSC_TX
x01
010
111

Sometimes you just need to look at a truth table to figure out what you really want. This is an OR, but with the !RESET pin inverted. Unfortunately, that's two different kind of gates, so that's two more chips. Surely we can do better.

Well, one thing that you learn is that an AND gate is the same thing as an OR gate where all of the pins are inverse. By the same token, a NAND gate is the same as an inverted-input OR gate. And, of course, a NAND gate with the two inputs tied together is an inverter.

So if we use an inverted-input OR gate, and want the !RESET pin inverted... well... the inverted input will do that for us. At the same time, we want the data to *not* be inverted, so that means if we're using an inverted input gate, we have to invert it again first.

So the final outcome is a dual two-input NAND gate chip. One gate inverts the TX line to make !TX, the other takes !TX and !RESET and inverted-input-ORs them together - and remember, an inverted-input OR gate is a NAND. Bazinga! One chip, and we have the truth table we want. While programming is taking place (and !RESET is low), the TX pin to the oscillator will be held high. Otherwise, the TX data will be unchanged.

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