I've found sometimes when cold-starting the frequency of a 5680A is unstable enough to sometimes result in the controller locking up.

This was worked-around on the ATTiny841 variant by clocking the controller internally until the oscillator indicated a lock and then switching to external clocking, but when we moved to the ATMega328PB (because of running out of flash) that wasn't an option.

I tried first to delay startup by holding RESET low with a Schmidt trigger buffer on an RC circuit, thinking that was the issue, but it didn't fix things all the way, so I've decided to replace that with a hardware watchdog.

The STWD100NPWY3F is a good choice. It's has an open drain output that it will bring low to reset the controller. It expects to see rising edges at least every 3 ms or so on its input or it will trigger a reset. An unused line on the controller will be configured as an output and every time we used to call wdt_reset(), we'll call a method that does that and toggles that output line. As long as we do that at least once every ms or so, that should be enough. If the controller gets wedged, then the watchdog will reset it. Fortunately, I've not seen a board lock up so hard that briefly shorting RESET to ground on the ISP header doesn't unstick it. The issue in the past has been sometimes it's hard to tell the difference between mode 0 and a locked up controller, so this will make that unnecessary.

As a happy coincidence, when programming the controller, RESET is held low anyway, so the fact that the watchdog won't be being petted during programming won't be an issue.

EDIT: It took a while, but I finally got around to building one of these, and I paired it with a cold 5680A. I was able to observe the controller go bonkers for a moment and - unlike in the past - it got reset and started right back up. Overnight, it made it to mode 3 and all indications are that it works perfectly.