a configurable 16-32 bits MPU in VHDL for tiny FPGA

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The microYasep is the first implementation of the YASEP architecture.
The microYasep is a minimal core so the post-update feature is not available but it's not critical for MPU applications that don't do memory-intensive operations.
Each instruction takes 2 cycles and the core fits in less than 400 lines of VHDL.
It can fit in a A3P060, MachXO2, ICE or other small FPGAs.
It's a great replacement for ARM/AVR/PIC cores and other proprietary architectures !
Oh and the IDE is totally written in HTML5... Write your application code, simulate, generate the instruction map and synthesize the VHDL code.

1. Current status

  • Current status

    Yann Guidon / YGDES07/25/2015 at 17:49 0 comments

    At this time, the YASEP project is in a broken state because of the deep change in the instruction format. The assembler must be totally rewritten. Without the ability to feed the core with clean instructions, it doesn't make sense to update the VHDL code (not a big work though).

    The YASEP2013 iteration contains an obsolete ISA that works and has been demonstrated but it would be unwise to base your project on a core version that will be shelved soon. Source code compatibility should be good however.

    The current priority is the rewrite of YGWM. Please help !

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