a configurable 16-32 bits MPU in VHDL for tiny FPGA
At this time, the YASEP project is in a broken state because of the deep change in the instruction format. The assembler must be totally rewritten. Without the ability to feed the core with clean instructions, it doesn't make sense to update the VHDL code (not a big work though).
The YASEP2013 iteration contains an obsolete ISA that works and has been demonstrated but it would be unwise to base your project on a core version that will be shelved soon. Source code compatibility should be good however.
The current priority is the rewrite of YGWM. Please help !