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YASEP Yet Another Small Embedded Processor

YASEP is the architecture/ISA of a 16/32 bits microprocessor that is original, Free, configurable, compact and ideal for DIYers, teaching...

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The YASEP is a CPU/MPU core designed for small footprint, good code density (avg. 24 bits/instruction), simplicity (orthogonality) and high memory bandwidth. One conditional instruction can trigger up to 3 data fetches and 1 data write, and update up to 3 pointers ! It is adapted to simple stream processing, basic graphics or the mundane tasks of a microcontroller.

A simplified version is implemented as the microYasep (https://hackaday.io/project/6909-microyasep ) which departs from the canonical MIPSy RISC architecture. The key is its 16 registers, including the instruction pointer and 5 pairs for register-mapped memory access.

The architecture is developped and matured using a HTML5 IDE (based on YGWM) that includes documentation, assembler, disassembler, editor, simulator, and much much more. Unlike other architectures, you don't need to install any software on your computer, you can start coding in

The YASEP started in 2002 started as a side-project, a hobby that has now turned into my first Mandelbrot-complete architecture. It has also spawned several sub- or side-projects such as HTTaP, YGWM and more (see my other projects).

The YASEP strives to be as free as possible (to the point of creating custom tools), small and simple (easy to understand by newcomers, uses as few resources as possible), hence as cheap as possible so it can be used anywhere, even for education (I'm looking at you, Arduino !)

All you need to get started is to point your browser at the HTML5-based windowed IDE. The last stable version is stored at http://archives.yasep.org/yasep2013/

Follow the tips, click around... It's all in your browser so you can't break anything (though you can lose your work). No per-seat fea or artificial limitation. You can hack (with) it !

You can start from existing code, edit your own version and simulate it ! (Code save and load are a bit broken but there are workarounds, please help me fix that). When you are happy with the code, it can be uploaded in a matter of seconds to a Flash SPI memory (this feature was then spun-off as #SPI Flasher).

In october 2015 I started a related project : #Discrete YASEP
It's a YASEP implemented with MSI CMOS chips for maximum visibility and insight into the guts of this architecture.


Logs:
1. Call for help !
2. ASIC

build_asm.sh

A script that downloads all the necessary Defora files and creates an assembler (for the pre-2014 obsolete architecture)

x-shellscript - 1.33 kB - 03/22/2016 at 11:41

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  • 440 × Time it takes a while
  • 1 × JavaScript because dynamic coding helps prototyping with fast turnaround

  • ASIC

    Yann Guidon / YGDES04/14/2016 at 23:07 0 comments

    A certain nasty, nasty guy here has put an idea in my head. Or more precisely, provided a link between an ooooold fantasy, and actual reality. Of course there is a high cost : a LOT of work and about $10K.

    Alexander has already gone through a MOSIS run with his ternary logic chip. He uses the full-custom way, making his own gates with MAGIC. He got 40 chips (and packaging + wire bonding is quite an expense too).

    But after the discussion I came with this thought : it is possible. I'm drooling. Given a well-designed core (a lot of work remains) it is only a matter of money to turn it into actual silicon. Money is not easy but I believe it's the least hard part.

    Now what would a MOSIS run look look ? A 16-bits microYASEP with a 40 pins DIP ceramic package, probably running at split voltages (3.3V for IO and about 1.8V for the core) with one external 16-bits bus, one SPI slave port for debug and that's all.

    Pins:

    • GND
    • Vio
    • Vcore
    • MISO, MOSI, SCL, SEL
    • Data I/O (0..15)
    • Addr out (1..15)
    • R/W, bank select (00: nothing, 01: program memory, 10: Data 1, 11: Data2)

    Total: 41 pins :-( I'll have to sacrifice one feature and there is not even a clock input... Maybe a PLCC44 package is possible ?

    The other concern is the SRAM. The current architecture relies on 3 banks of dual-port SRAM and without onchip memory, the core will be dog-slow... So one critical goal is to target a relatively recent process to get enough memory (180nm ?), plus finding optimised SRAM array blocks.

    For the workflow, I'll try to hack an existing synthesiser in order to translate the VHDL code into a correct netlist, then it's a matter of manual place&route. Anyway the YASEP is small and a manual translation is easy.

    It doesn't look obvious but most of my efforts, advertised on HaD and other places, are meant to lead to this. A first silicon chip. I have the roadmap and I'm investing my time, energy, money and the rest into it. But I also enjoy every step that takes me toward this goal and I'm glad Antti brought me to HaD.io !

    Thanks for reading this rant, you can now resume your normal activities.


    Edit : The serial clock could be shared with the core clock... I could reduce the address width but it would cripple the core :-/

  • Call for help !

    Yann Guidon / YGDES07/25/2015 at 16:17 0 comments

    I need your help !

    The YASEP has hit a wall in 2014 as it has grown too much for it infrastructure.

    I have now split the original project :

    * The YASEP is the architecture and processor-centric development. That's here. The instruction format changed in 2014 and is now frozen but the whole system must be updated. Several tools are broken.

    * YGWM is "whygee's window manager", which has grown beyond expectations and my coding skills. It becomes a side project on its own so it can be reused for other architectures and projects.

    The priority now is to review and re-code parts of the YGWM framework. I need help from JavaScript experts to integrate newer HTML5 features and apply professional coding practices.

    Whowants to play with my window manager's code ?

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