07/25/2015 at 16:17 •
I need your help !
The YASEP has hit a wall in 2014 as it has grown too much for it infrastructure.
I have now split the original project :
* The YASEP is the architecture and processor-centric development. That's here. The instruction format changed in 2014 and is now frozen but the whole system must be updated. Several tools are broken.
* YGWM is "whygee's window manager", which has grown beyond expectations and my coding skills. It becomes a side project on its own so it can be reused for other architectures and projects.
Whowants to play with my window manager's code ?
04/14/2016 at 23:07 •
A certain nasty, nasty guy here has put an idea in my head. Or more precisely, provided a link between an ooooold fantasy, and actual reality. Of course there is a high cost : a LOT of work and about $10K.
Alexander has already gone through a MOSIS run with his ternary logic chip. He uses the full-custom way, making his own gates with MAGIC. He got 40 chips (and packaging + wire bonding is quite an expense too).
But after the discussion I came with this thought : it is possible. I'm drooling. Given a well-designed core (a lot of work remains) it is only a matter of money to turn it into actual silicon. Money is not easy but I believe it's the least hard part.
Now what would a MOSIS run look look ? A 16-bits microYASEP with a 40 pins DIP ceramic package, probably running at split voltages (3.3V for IO and about 1.8V for the core) with one external 16-bits bus, one SPI slave port for debug and that's all.
- MISO, MOSI, SCL, SEL
- Data I/O (0..15)
- Addr out (1..15)
- R/W, bank select (00: nothing, 01: program memory, 10: Data 1, 11: Data2)
Total: 41 pins :-( I'll have to sacrifice one feature and there is not even a clock input... Maybe a PLCC44 package is possible ?
The other concern is the SRAM. The current architecture relies on 3 banks of dual-port SRAM and without onchip memory, the core will be dog-slow... So one critical goal is to target a relatively recent process to get enough memory (180nm ?), plus finding optimised SRAM array blocks.
For the workflow, I'll try to hack an existing synthesiser in order to translate the VHDL code into a correct netlist, then it's a matter of manual place&route. Anyway the YASEP is small and a manual translation is easy.
It doesn't look obvious but most of my efforts, advertised on HaD and other places, are meant to lead to this. A first silicon chip. I have the roadmap and I'm investing my time, energy, money and the rest into it. But I also enjoy every step that takes me toward this goal and I'm glad Antti brought me to HaD.io !
Thanks for reading this rant, you can now resume your normal activities.
Edit : The serial clock could be shared with the core clock... I could reduce the address width but it would cripple the core :-/