I found something interesting when reflow soldering. Don't allow solder paste to get inside drill holes that aren't copper filled (for example tabs with drill holes on panelised boards). It turns out the solder hardens on the exposed sections of the holes and the internal unflown solder explodes out and sprays onto the surrounding parts from the expanding flux gases. The casualty radius was about an inch around from a small 0.3mm hole.

So if you get solder paste in there (I got it in there when cleaning off smudged solder), clean it out thoroughly. A piece of thin wire should get most of it.

If you don't, you will have spotted solder all over the place on parts and pads.

Recently, there was a blog post about PCB design guidelines to minimize interference and emissions - http://hackaday.com/2017/01/26/pcb-design-guidelines-to-minimize-rf-transmissions/ . Not only that, but I've found this gem in the comments - http://www.hottconsultants.com/tips.html It looks super useful, just has too much information for me to understand how useful exactly it is =)

I have added all three to the project's external links...

Two more to add - today I was re-reading this: http://hackaday.com/2016/03/17/so-youre-scared-of-surface-mount/ and there was this site linked: http://www.surfacemountprocess.com/ , which has some very useful information on nuances of SMD and the basics (while being a site endorsing a service, it's rarely mentioned and is a very good site overall, I learned a lot).

Maybe make a separate post with external links? I'd make my own and update if  if you're not against it, kind of "Arsenijs' links about PCB design and short summaries", any contributor could keep their own post here if desired (since one can't edit a post which he isn't the author of, so there can't just be a "Links" post any contributor of this project could edit).

Useful List of Useful PCB design tools by @coletonn - https://hackaday.io/page/2722-useful-list-of-usefulness-pcb-design-edition

My current job was my first experience with real PCB design, and I've learned a lot. Probably the biggest lesson has been to not underestimate trace impedance. On a 1" square PCB, I had a 15mil GND trace going around the edge with short branches connecting to components. The result was a very unstable buck converter that needed a jumper across the board.

When I started with PCB design I thought it was only about connecting the points however way possible. How I was wrong. And now the more I learn the less I know. Every little detail can make or break the work, but it is always exciting.

Excellent guidelines. Personally, I try and avoid using traces less than 13mil unless I have to for fine pitch components etc. I avoid right angle turns due to a) aesthetics and b) right angle corners can peel away from the PCB substrate easier than say, 45 degree corners can. 

But definitely place your components into functional groups, e.g. switchmode supplies, DAC/ADC subcircuits etc. I generally place connectors first to determine the outline of the board (observing sensible separation between digital and analogue connectors etc), then place my functional groups, as close to their relevant connectors as possible. Also, put in filtering and other EMI/EMC measures at the schematic stage, even if you don't end up populating them later. Easier to add a footprint for an ESD-protecting transorb, or a common-mode choke, at the schematic stage, than try and kludge it in once you're building the PCB!

If it's a complex new design, add low-value resistors in the various power supply sections so you can a) do current measurements for the various circuit sections and b) remove power from sections of the board for tracing that power supply short...

And ALWAYS use a ground plane, and a power plane!! And decouple. DECOUPLE! 1n, 10n on digital supple pins. 100n, 1u near the IC. 10u caps etc sprinkled around the board.

Ok, I'm a bit drunk so I'll stop now.

Thanks for your input. Good pints. Definitely the mechanical design has its weight on the PCB Layout (Connectors, Switches ....). 
I think 13 mils is bit too conservative. If you have a big number of nets/pads then it will be real hard to finish the routing.

"8 mils clearance for traces and 10-15 mils clearance for shapes (copper pours)" Why this constraint?  You mean that it's ok to put signal carrying traces close to each other but they need to be kept  far away from static copper (pours are usually gnd/vcc)....

I think he is a bit too conservative.  My el cheapo Chinese proto PCB place recommends 8/8 rules, but claim they can do 6/6.  Their DRC checks for 6/6. 

For simple boards, I have pushed 6mil track to track.  This is what can happen when I tried 6 mils on fills.  They fixed a short by hand - probably found that on eTest.  That was the only 1 out of the 10 I have ordered.

So now I know better.  I am using 8 mils to trace/fills.  If I need density, I would go 6/6 on traces on proto.  I am used to etching my own boards, so shorted/voids are no big deal to me.

This is my first board there a year ago.  They passed their claim what what they can do.
https://hackaday.io/project/1347/gallery#e6979505034cefdbf5fd2597afbda724

This is what I have seen this year.  
They have improved on the solder mask, but getting worse on silkscreen.  I am at a point that I have removed silkscreen on small parts and only use it for labelling.
https://hackaday.io/project/4993-dual-channel-battery-chargeranalyzer/log/17291-keeping-up-with-the-times-prototyping-with-qfn-and-bga

One thing i would add in here is the IPC organization (www.ipc.org) and maybe describe roughly what they do, and why industry standards and rules can help you and should be used to get your design right the first time. 

Something else that i kinda missed in your text is the importance of signal speeds, rise times, impedances and stuff like that. Identifying critical signals (like clocks, reset lines,...) early in the design and make them a priority in component placement and signal routing helps a lot to get a reliable design. Especially the rise times of digital signals getting shorter and shorter is something easily overlooked, and i expect more and more problems there with microcontroller clock speeds increasing.

You kinda scratched that topic a little bit, but i think you should elaborate some important parts a bit more. In the EMI chapter, one basic thing you have to keep in mind is that both high immunity and low emission is the key to success and you have to think about that while layouting too. Do i have a signal that is sensitive and needs to be protected, or do i have a line with lots of potential noise that needs to be isolated and removed? Your sentence about the series resistor: "Series resistors should also be placed next to the micro-controller pin that they connect to." can be correct, or completely wrong, depending on the signal. Please change that and try to explain why signal termination is important and maybe show some termination circuits. Once that theory is known, the layouter should understand where exactly (source/sink) and why the terminations have to be placed.

I'll try to give some more inputs and feedbacks along the way later on.

""The layout person asked me about prioritizing which passives should be
the closest to a large chip.  I told him smallest values first.  He
smiled at that."
I smiled at that too !!"

Smiling is nice, but understanding that the lowest capacitor value, combined with the lowest trace impedance and resistive losses gives a much better high frequency blocker, and that the lower frequency signals "care less" about impedance thus allowing the bigger capacitors to be placed futher away goes a long way. ;)

I think you raise good points. Would you be interested in adding yourself to the project and making the fixes ?! I think you have a bigger knowledge about the parts you wat to add . and you have cid+ I think you will be great addition to this project.

One major issue with IPC standards is that their specs are not free.  So you'll either need to have access to it from work or manage to find the specs somewhere tugged inside a board house's app note or someone's website.  If you do a board layout using a board house's DRC, chances are that they already incorporate some of the IPC's recommendation and the board vendor's tweaks for their process to get good yields.  So that part is actually easy.  It however may not be blessed by the CM assembly house which have to place the components or rework on them or the test requirements.

There are a whole lot of signal integrity topics that can be included, but I doubt the majority of readers would bother with those.  The other thing is that it is a topic that unless you understand completely, giving the usual thumb of rules without understanding the limitations cause more harm than help.  Once you get those "I know Kung Fu" people on youtube, then the rest of the noobs get the wrong info.  I have seen and try to correct way too many cases of people trying to do monkey see monkey do - track matching without a clue what is that they are trying to match against or when to use them.  Yes, it might look cool, but not effective engineering.

BTW when I said it feels like Zen Q&A - meaning that the answer to a complicated question is a simple one.  The layout person is smart and experienced enough to ask that question in the first place.  Trace/via parasitic can contribute a lot more on smaller component values than large ones and hence my answer.   It also applies to resistors (except 0 ohms jumpers etc) /cap.

found this: http://in5d.com/97-spiritual-enlightenment-stories/  for "Zen Q&A"

Story#3 is my point to the "monkey see monkey do" issue.

That is why I smiled also. A smart simple answer right to the point. I like it :).

IPC is closed that is right, but I think it should be mentioned. Maybe also mentioning CID and CID+ programs for the readers. There is also PCB Library Expert which will calculate footprints based on IPC and it is free. But no love for KiCad nor Linux.

I like these comments, very informative :)

I do agree that access to IPC standards is not in the reach for most of us, but i think even knowing about the ressource and knowing that there is something trying to bridge the gap between digital design and the physical world can be helpful.

And about signal integrity topics, i do understand your point of view too that this field is so broad and complex you simply can not learn it by reading a few chapters in the internet. I think what is important is first and foremost that designers are made aware of the problem. Try to explain the importance and relevance not only for your design to actually work as intended, but also what consequences (emission/immunity) this can have for your design. My idea is not to write "A complete guide to Signal Integrity" but to try and show some of the basics, and try to give an outlook into the richness of the topic and where/when you should probably start to dig deeper into the topic or ask a specialist, before you even start to think about drawing the schematics of your circuit.

Agree on the part: You shouldn't even try to draw schematic until you have done the analysis.  I have added SI mailing list & Dr. Howard Johnson's Signalintegrity.com site to the project detail.

Most HaD reader don't even understand AC analysis, parasitics and the most basic electronics and still stuck playing with breadboard and asking for DIP packages, so the whole complex SI escape their little comfort zone.

No two SI experts can even agree on the topic of decoupling.  You either pick one or the other and don't try to mix them as that will cause more problems that you are trying to solve.  A little knowledge without knowing your own deficiency is a dangerous thing.  So you have the choice of the blue pill or the red pill.  i.e. either go in with the intention of learning all you can and forever change your view of the world or you stay ignorant and be happy.

Two of the almost Zen Q&A moments as people asked me about placement on the spot:
Supplier asked me the orientation large MLCC cap on a module.  I told him that it should be on the use the shorter axis - less flexing/less cracking.
The layout person asked me about prioritizing which passives should be the closest to a large chip.  I told him smallest values first.  He smiled at that.

"The layout person asked me about prioritizing which passives should be the closest to a large chip.  I told him smallest values first.  He smiled at that."

I smiled at that too !!