The TIS-100 is an "interesting" multi-CPU computer used in the game TIS-100. There are computing nodes and stack nodes. Computing nodes have on directly addressable register, one backup register, a zero register, four ports to surrounding nodes, and can only perform additions, subtractions, jumps (conditional and not), and moves. All interactions with the four ports are blocking until a response from an adjacent node occurs. The stack node just acts as a stack serving read and write requests as they come. I plan on working on this project from many different directions; using ATtinys for each node and serial data transfer, using FPGAs using serial and/or parallel data transfer, etc. The only main goal is to recreate the function of the TIS-100 and try to keep the cost for each node as low.
Currently I am exploring basing each node around a ATtiny85 as it has
just enough I/O pins to create a serial communication to each of the 4
ports separately. Each port can be turned off and on separately simply
On another branch of thought I am looking at
producing each node on a FPGA, maybe utilizing the DIPSY FPGA project
here on Hackaday.io.