Hardware is slower

A project log for FPGA Serial Terminal

Instant-on VT100-style serial terminal implemented in minimal FPGA board, with VGA display and PS/2 keyboard.

Howard JonesHoward Jones 10/10/2015 at 11:182 Comments

Things have slowed down a little with the terminal - partly due to the need to actually create something physical next. I've decided to learn how to etch my own boards, and make a little breakout PCB for the serial, VGA and PS/2 connections. Partly because I'll need them for the final target FPGA board, and partly because the dev board I do have seems to have something strange with the serial port. With my bus pirate, I can see traffic from the uart on the right pins, but somehow that doesn't actually appear on the db-9 connector at the edge of the board, and hence doesn't reach the PC. So I'll be using some GPIO pins and a breakout to make a serial port that I know for sure how it works. It looks like I will need an external 1.8432 MHz oscillator to get selectable baud rates, too - the onboard PLL can't generate that from the 50MHz system clock. You can get some serial clocks (e.g. 19200, 9600) OK, but I'd rather have the UART baud rate register work properly so it's all software-selectable!

On the HDL and software side, there's a makefile to build the z80 firmware and the FPGA bitstream now. I finally fixed the annoying whistling noise from the dev board, and the Z80 does some more self-test now. I really need the I/O to get further - keyboard in, and serial i/o - so I've got a cheap UV exposure box ($15 from ebay, intended for curing nail varnish), a little chemical kit, and the free version of diptrace. Time to ruin some 2-inch squares of FR4...


Xark wrote 10/10/2015 at 21:49 point


I have been following your project since I have a fondness for old serial-terminals (I used a DEC one as pictured at one time) as well as FPGAs (which I find very fun to work with).

I wanted to mention that I think adding a special oscillator for a UART clock is probably not really needed.  If you have a 50MHz system clock this should provide more than enough accuracy for standard baud rates.  For example, 115,200 bps works out to 8680.555... ns per bit.  If you use a 50MHz clock counter and count to 434 (50,000,000 / 115,200 rounded) you get 8680 ns which is really close (and plenty accurate for a UART which can typically tolerate  < ~2% of inaccuracy in my experience).  Typically you make the "counter max value" programmable and then you can support "nearly any" baud rate by setting this to the right value (i.e., clock / bps). I have built several FPGA UART designs that operate this way and they work great (and FPGA designs with multiple clocks and crossing clock domains are tricky - so best avoided).  If you want to see an example, I found this one to be pretty good 

Nice work and good luck on the project!

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Howard Jones wrote 10/10/2015 at 22:33 point

Thanks for the advice! I came to that conclusion after trying to get Altera's PLL wizard to generate clocks for me, and it refusing. I assumed it was going to be more creative than me about it... should know better, really.

The T80 cpu comes with a 16450 UART core, which takes a 16x115200 clock to generate all the standard baud rates (hence 1.8432 Mhz) - a mod 271 counter looks like it will get me well inside 2% of that target. My own actual use case is mostly 9600 for cisco consoles, but I'd like to get as much of the typical VT functionality in there as I can - my own happy memories are mostly vt220 and vt320, which were packed with extra features, relatively speaking. I think if it will run Emacs and Nethack and a few of those animation demos, I'll be happy :-)

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