There's a github repo with my VHDL code in it (and eventually the Z80 assembly too): howardjones/fpga-vt. It's my first attempt at an HDL implementation (or any significant-sized digital logic actually, I'm a software person), so please be gentle.

Today's software vs hardware lesson: I already knew this at the back of my head from writing 68k assembly years ago, but I noticed that my Logic Element usage on the chip jumped up from 200 to 1600 some time recently. Looking at the RTL, I found a massive array of logic gates eventually feeding into the 'flash' flag (which is ANDed with the actual pixel to decide if the foreground or background is shown on a flashing character). Why? because I have a counter to count frames ("jiffies") and used that to decide if the cursor or character flashing flags need to toggle. I wanted them to flash at different rates so that the cursor wouldn't get lost. My rates were "mod 27" and "mod 36". Switching to 24 and 32 saved 1400 LEs, or about a quarter of the entire FPGA (roughly 5000 LEs on the target board, 8000 on my dev board).