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First successful decoding of 3R stream in VHDL

A project log for Recursive Range Reduction (3R) HW&SW CODEC

A high speed circuit design in JS and VHDL for decoding 3R bitstreams, a "quasi-entropy" code that compacts series of correlated numbers.

Yann Guidon / YGDES 08/29/2015 at 04:280 Comments

I got the core part of the system working a few minutes ago :-D

More internal details will follow in the coming months.

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