Recursive Range Reduction (3R) HW&SW CODEC

A high speed circuit design in JS and VHDL for decoding 3R bitstreams, a "quasi-entropy" code that compacts series of correlated numbers.

test_dec3r.vhdl This testbench exercises the 3R decoder. it also shows how to interface it with other blocks. You'll want to look at it when the rest compiles. x-vhdl - 3.04 kB - 04/14/2016 at 05:41		Download
dec3R.vhdl The decoder. Sorry for the comments in french. x-vhdl - 5.88 kB - 04/14/2016 at 05:37		Download
bram.vhdl A generic 1-port BlockRAM for storing the stack x-vhdl - 1.13 kB - 04/14/2016 at 05:32		Download