New CPU design, mass storage problems

A project log for FPGA computer

I am building a (currently) 64k RAM computer with an FPGA. Now with lots of pipelining!

dylan-brophyDylan Brophy 04/02/2017 at 20:400 Comments

My old N-Series CPU design is an incredibly inefficient CISC architecture that is no doubt super slow just due to the number of clock cycles and unnecessary memory accesses per instruction. I'm going to create a new architecture that supports more memory and is hopefully much faster (133 Mhz???).

The reason I haven't updated this project much in so long is because I ran into some mass storage problems. The FPGA board I'm using has 3 places to store non-volatile data. After an attempt at every. single. one, I needed a break. Its a bit frustrating when not even parallel NOR flash will work right, after trying SPI eeprom and the FPGA's own non-volatile storage. Any advice would be appreciated, by the way.