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A project log for FPGA-based GPU as high speed learning platform

FPGA-based GPU and sprite engine with burst optimized design, implemented across several FPGA platforms and memory systems.

Ian HanschenIan Hanschen 11/01/2015 at 03:150 Comments

I figured if I had the GPU use the SDRAM, and let the display scan out of SRAM, I could avoid bottlenecks for display scanout. But there's still contention to copy from SDRAM to SRAM when the framebuffer is dirty, and if I let the LCD scanout have bus priority it takes a good 5 seconds per frame update..

Going to try inserting a FIFO into the display scanner that charges from SRAM,, with the display running at a fraction of the speed of the memory bus.

Update: With a scanline buffer it's significantly faster but still has a bit of a boxcar effect.

update: fixed the tearing a bit:

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