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Discrete YASEP

a 16-bits YASEP computer (mostly) made of DIP/SOIC chips like in the 70s and 80s... with 2010's twists!

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I've long wanted to implement the YASEP architecture such that all the internal structure is exposed, visible, accessible !

The YASEP is a rather simple RISC design and a functional computer system based upon it needs a handful of PCB using mostly medium scale integration ICs (74HC245 etc.). It is meant to have some of the charm of the homebrew computers of the 80s with the benefits of the 2010s technology (RAM is made of single chips, total power should be less than a few Watts, uses tons of dirt cheap miniature surface mount devices...). Yet, I want to avoid "black boxes" so I try to only use fixed function circuits.

I don't think it will run fast, maybe around 1 or 2 MIPS. If you want speed, much faster versions can be programmed into FPGAs! But you will not "see" anything.

Today, can we still design cool stuff without a FPGA or microcontroller ?


Have a look at the little brother of this project : #YGRECmos !


I have been teased by many BMOW like MyCPU80, the #The T-1: A discrete 8-bit Stack Computer, the #Fourbit, the #AYTABTU - Discrete Computer... (to name only a few, the list grew so much I had the create #Hackaday TTLers)

I felt the need to restart this project of a DIP-based minicomputer, like I imagined when I started the YASEP project more than a decade ago. Except that now, power consumption and parts price should be kept low, all the parts should also be available in SMD package because the final version will be on flexible PCB !

This is so ambitious that I must start and spin-off several sub-projects like #PICTIL, #Low-resolution scanner for cheap data input or #DYPLED ...


General architecture

The architecture is adapted from the #microYasep where instructions take two cycles. It has a characteristic "2 reads - 1 write" heterogenous register bank that is accessed once or twice for each instruction depending on its length.

The following picture shows the datapath of the microYASEP and its two phases. The general organisation is preserved but the design will be split in a totally different way.

There are 3 memory banks, each 32K*16 bits and dual ported :

  • Instruction space
  • Data bank 1 (usually: working memory)
  • Data bank 2 (usually: stack and stack frame)

(a 3rd address bus is MUXed for convenient debugging)

A custom, internal bus is being defined, which connects all the boards :

  • user/control panel (read and write registers in hexa, connect to a host computer)
  • Debug (trace, breakpoints, perf/events counters) [optional in the final version but life-saving during development and factory tests]
  • register set (R2, R3, R4, R5) (or should I say "counter set" ?)
  • Memory bank 1 (A2/D2, A3/D3)
  • Memory bank 2 (A4/D4, A5/D5)
  • Program memory (PC, R1, as well as A1/D1 to read/write instructions)
  • ALU (also gives access to the SR and I/O spaces)
  • Control/decode/sequence logic
  • Memory editor / instruction assembler (optional too)
  • Framebuffer (LCD and/or VGA output)
  • Sound in&out, joystick
  • User circuits, breadboard zone (so you can add your own devices)
The "bus", accessed along the edge of each double sided board, contains at least those signals :
  • Result (DST="destination") : 16 data bits, 4 address bits, 1 strobe signal => writes data to one of the 16 registers
  • SND and SI4 : 16 data bits, 4 address bits => read the 16 registers
  • Current Instruction word (16 bits)
  • Current PC
  • Auxiliary address bus (for debugging/memory edition)

However it is not meant for I/Os, only for architectural exploration and debug. The ALU has the logic that deals with instruction operands and format so SR and IO are connected there.

Each board's size is "double Europe" (160×200mm) and is paired with a neighbour (hence the A and B suffix). Pairs of boards are connected to the others with through-board pins.

Most buses use "3-state" logic to multiplex data, which is not ideal but saves some complexity.

Power supply

Hopefully the final version can be powered from a USB port so the power envelope would be 5W. An additional power input might be necessary though. The prototype has some DIP chips that need 5V but the whole system will be 3.3V in the final version. DC/DC converters are used and a mix of HC, HCT and LVC parts translate logic levels.


Logs:
1. First page and first roadblock
2. Board 1 : the user interface
3. Board 2 : Register set
4. Board 1 : the user interface (second take)
5. Design of the input FIFO
6. Clock generation circuit
7. The progress so far
8. Keypad musing
9. Emulation
10. Command and control as ASCII bytes
11. Asynchronous serial reception
12. User Interface Board overview
13. "Redneck" disintegrated 7 segments decoder
14. Keyboard proof of concept
15. Pulls!
16. Dear SN74HC688
17. Single stepping and scroll wheels
18. Sunday bug mouse (Sun debug mouse)
19. Parts, parts, parts...
20. Even better hardware debugging
21. Random Available Memories
22. DILosaure rising
23. A better...

Read more »

CY7C1020V.pdf

32K×16 Asynch SRAM, TSOP II 44, 3.3V

Adobe Portable Document Format - 177.00 kB - 01/10/2016 at 15:47

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74HC193.pdf

4-bits up/down counter with preload input

Adobe Portable Document Format - 179.16 kB - 01/10/2016 at 11:54

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74HC283.pdf

4-bits full adder

Adobe Portable Document Format - 111.20 kB - 01/10/2016 at 11:53

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74HC153.pdf

Dual MUX4 with enable

Adobe Portable Document Format - 173.00 kB - 01/10/2016 at 11:50

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74HC253.pdf

Dual MUX4 with tristate output

Adobe Portable Document Format - 145.78 kB - 01/10/2016 at 11:48

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  • 80 × 74HC253 (for the bus) dual 4-to-1 mux with tristate output
  • 40 × 74HC153 (for the SHL unit) dual MUX4 with enable/AND
  • 44 × 74HC193 (for the register set) 4-bit synchronous binary up/down counter.
  • 6 × ASRAM 32K×16 (and more for the debug features)
  • 16 × 74HC138 used everywhere...

View all 9 components

  • Prior art

    Yann Guidon / YGDES05/21/2017 at 21:15 12 comments

    I've been hinted at this 43 years old project from Elektor:

    https://archive.org/stream/Computer74/computer-74

    It's exciting that this idea has been in the air for so long, and yet we don't see it widely spread...

  • Got the backbones too

    Yann Guidon / YGDES10/21/2016 at 12:17 0 comments

    After Progress, at last !, I went looking for "ribs" (or "fishbones") or the backbone of the system.

    I found extra-long pins on eBay in sufficient quantities, smaller than what I have in stock but still enough to stack 5 pages. It should be enough for the first implementations...

    The main PCB could serve as P1A/P1B... or something else requiring a rigid/solid base, connectors etc. so that makes 6 pages.

    I received samples from Würth Elektronik !

    Thanks to the cool rep, we found a reference that is longer than the previous ones, almost 40mm (so the above picture is a reminder for the reference for a next order)

    I might have also found very interesting prototype boards that can be slightly bent...

  • Give that man a cookie

    Yann Guidon / YGDES05/08/2016 at 04:48 0 comments

    It all started in january 2016 with a suggestion to @Stefan Lochbrunner about a new #Breadboard Widgets module (see the comments).

    He quickly created a nice board layout, which he uploaded to his git repository.

    And some days ago, I received this :

    (I'll have to test them now)

    Thank you so much, Stefan, I owe you one #DYPLED (once it's working) ;-)

    That, the #PICTIL story and other personal experiences, confirm that German hackers are among the best ;-)

    Someday I should make a similar breakout board for the Flash chips that I use in #DYPLED (see the yellow adapter board in Stack-based programming, which is nice but expensive and quite large)

  • Progress, at last !

    Yann Guidon / YGDES05/03/2016 at 00:47 0 comments

    A few things have kept this project from flying higher...

    • work
    • other projects (damn, 33 now ! am I bulimic ?)
    • the multiplexing logic of P1A
    • board-to-board SMD connectors (I don't have the matching connectors and they are pretty expensive but I need a significant quantity...)

    The last problem seems to be solved, while cleaning up the workshop...

    I found a decent supply of 2×16 SMT connectors. They are pretty low-density but the 2.54mm pitch is good anyway. Contrary to the expensive FX8-100P, with the 0.6mm pitch, it is possible to run traces through the pins so all the signals are used, instead of just one half.

    I bought the matching male and female pairs on eBay, many years ago:

    They are about 8mm high when connected:

    8mm is a bit too high. However the receptacle alone is 3.7mm high. Add a Kapton foil and that's 4mm.

    The main board will have a lot of long pins to stick through all the pages. With 40mm pins, that's about 10 pages. I'll have to find longer pins but they might be found for wire-wrapping and such. That will be my next eBay search.

    Until then I can prototype up to 5 pages with the pins I already have in stock.

    It's possible to cheat a bit by removing the black spacer after the pins are soldered, which makes 6 levels. I have other pins (more numerous) that can do 4 levels, eventually 5:

    Now, the question is : how many of these 32-pins connectors does one page need ?

  • Displaying the register name

    Yann Guidon / YGDES03/08/2016 at 23:07 0 comments

    With the experience gained from de #DYPLED subproject, I can easily design custom LED displays and the register names (on the P1B board) is a great application of the principles. The ingredients are the same : a large parallel Flash chip (1M×16), 4014 type LED (long, narrow and thin) for the segments, some multiplexing (one 2N7002 for the low-side driving of a group of LED), a binary counter to sequence all that (taken from the main clock divider) and one mode bit (to select between hex display and symbolic name).

    P1B displays 3 buses: the result bus and the SI4 and SND source values. That's 3×4 bits. Add 2 or 3 bits for multiplexing, one mode bit and the address bus is under-utilized.

    The 16 bits of output are used for 2 7-segments displays, leaving 2 unused bits. I'd like to "save" one more bit so the Flash directly drives the MOSFET's gate and saves a demux chip.

    The rightmost digit displays the usual Hex numbers. The leftmost displays only 4 symbols, necessary to write the names Ax, Dx, Rx and PC. There should be a way to save a bit somewhere.

    A first visual examination shows that the A and F segments are on at the same time so they can be wired in parallel. This saves the needed 3rd bit, without having to resort to external logic gates. Furthermore, the segment D is the inverse of the segment G but this would require an inverting gate.

    In the end, decoding the register names uses only one Flash chip and 3 2N7002 :-)

  • Inspiration

    Yann Guidon / YGDES01/29/2016 at 23:25 0 comments

    I visited Labitat today

    https://hackaday.io/hackerspace/4882-labitat

    My host Christian was excited to show me a book-like box. And guess what ?

    The MPF-1 is not a book, it's a computer. Which is more or less my intention with the Discrete YASEP...

    Can you believe it's still manufactured and sold by Flite ?

    I hope to add a MPF-1/88 to my collection, to remind me where the inspiration comes from and what to get "right", such as the programming interface :-)

    The ability to assemble instructions without the need of manual assembly is precious. Typing hex codes is geeky but that's not an end in itself !

    I have noticed that the best development tools for a computer are also the tools that helped design it. With an open sourced design, both are the same and this makes the system even better :-)


  • How to verify actual timings and delays

    Yann Guidon / YGDES01/15/2016 at 10:27 0 comments

    As the system becomes more complex, it's trickier to evaluate the actual propagation times of the signals. Datasheets can't be relied upon because of the variations between manufacturers and batches, the PCBs add capacitance and we never know anyway.

    The only way to know is to measure. Inject signals at the input and measure the delays with the scope. But it is still pretty tricky because there are combinational and sequential logic stages, and not all paths have the same lengths, so a little signal could influence the propagation time of the whole rest. Think about the carry input of the ALU, or the control signals of SHL unit.

    My solution is almost simple and it requires the fabrication of a special circuit. A huge LFSR made of a lot of of shift registers (74HC164 for example) and some XOR gates. For suitable LFSR polynoms, look no further than http://ygdes.com/GHDL/lfsr4/

    The clock input can be selected from several oscillators, and the LFSR output are scrambled/shuffled to randomize a bit the generated bits. Each output of the examined circuit can be checked with a 'scope and jitter can be measured. Since the project is a 16-bits CPU, it's easy to cycle through the 64K input combinations and see "offending" (lagging) signals a few times per second, which is suitable for visual observation on a 'scope.

    From these observations, subcycles from the main clock can be allocated for each unit. For example I'm curious about the REAL propagation time of a carry through a chain of 74HC193. I can only estimate the time with the datasheet but the real delay will influence how long the instruction time will take.

  • Clocking: the revenge

    Yann Guidon / YGDES01/15/2016 at 10:03 0 comments

    There is a tie between the 24.576MHz and 18.432MHz source frequencies.

    The higher the frequency, the better resolution for scheduling the sub-cycles of each instruction. Finer sub-step allow a faster execution.

    24.576MHz allows 40.7ns steps, but it is not as handy as 18.432MHz to derive "useful" frequencies, for serial communication for example.

    I have ample supplies of both frequencies. 24.576MHz is desired but how can I extract the 3.6864MHz that is used by the other circuits ?

    24.576/3.6864 = 6.6666....

    Actually it means : for every 20 cycles at 24.576MHz, there are 3 cycles at 3.6864.

    You can substitute "transition" for "cycle" and it becomes pretty interesting, from a logic circuit perspective. A 74HC4017, a 74HC74 and some AND/OR gates will do the trick.

    First, the 4017 will turn on one output every 10 cycles. One cycle is 2 transitions, right ? So one 4017 can work with 20 transitions. Each transition can be identified with a AND gate between the 4017 output and the clock signal (inverted if necessary).

    One can evenly divide 20 by 3 with the intervals 7, 7 and 6. 3 AND gates are used to combine the 4017 outputs with the (inverted?) clock signal. The result is ORed and privides 3 pulses every 10 cycles.

    The pulses clock a 74HC74 with the /Q output looped back to the D input, which makes a cleaner 3.6864MHz signal (with some jitter).

    Did I mention that I love the 4017 ? :-)

    This circuit is rather easy to build with discrete parts but I might have to use a CPLD or tiny FPGA for the sequencing logic, because the timing gets pretty critical. I wish I could reach 4MIPS, that's 6 sub-cycles @24MHz and only 4 @18MHz

    Another interesting property of 24.576MHz is that it is a multiple of 2^16 (3×125×65536) and it's handier for power-of-two real-time scheduling (more on this later). OTOH 18.432MHz is "only" 16384×1125.

  • And now, the joysticks

    Yann Guidon / YGDES01/13/2016 at 20:10 0 comments

    As I'm contemplating the sound input and output, I deal with ADC questions.

    Since I'm able to digitize with 8-bits resolution at pretty high speed, I can also digitize at lower speed, position sensors for example. Several years ago, I played with those flat "thumb joysticks" made for the Sony PSP and they fit this project nicely.

    So I'm adding this new feature to the specs : 2× X-Y analog thumb controllers with 8 bits resolution. The 4 values will be available in the Special Registers space. I'm not exactly sure yet how I'll deal with the button calibration (center value) but it's not as if nobody had to solve this before.

    Looking more at the PSP, its screen is pretty cool too, 480×272px with 4.3" diagonal. That's not impressive but already good for $10. It would match my 1MB SSRAM budget, with a virtual framebuffer of 1024×512 for a nice scroll margin. No double buffering, though. The CPU is not fast enough to refresh everything in 20ms...

  • Board-to-board connection

    Yann Guidon / YGDES01/10/2016 at 11:43 4 comments

    The final design will use the 100-pins Hirose FX8-100 connector. The PDF contains these pictures, to give you a rough idea :

    The stacking height is only 3mm between two boards. Actually it will vary because the PCB wil bend ;) but pairs of PCB can be easily mated and moved up/down the stack as needed, that's important for modularity and repairs.

    Why this connector in particular ? Well, in another life I was a ETX PC/COM format enthusiast and by chance I got a half-reel of FX8-100S-SV from eBay (this can happen why you buy a box with "various parts" that the seller has no idea what they are or why they are useful and can't list what they sell... you're never safe from a good surprise !)

    Since this connector is used for the ETX COM format, availability is rather good. It has a lot of pins and the stacking height is about the thickness of SMD parts such as SOIC ICs.

    Now let's see the little issues :

    • The pin pitch is .6mm, it's not extremely thin, but thin enough to prevent wires from crossing from one end to the other with a standard 150µ etching rule. 150µ wire width and spacing is ok to run 2 wires in .6mm but there is no room left for the vias. The approach today is simple : use 2 contacts for one signal, so only 50 signals are available. This increases the number of required connectors... Maybe 3 or 4 are necessary.
    • I only have S-type connectors (a few hundreds). The complementary P-type is harder to get. I'll be investigating in the coming months, to find decent prices (sub-$) in medium volume. It seems that compatible connectors are made by another manufacturer, that could be a clue...

    When I have enough male/female pairs, I'll start designing a support board and generic flexible "pages" :-)

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Discussions

James Newton wrote 08/07/2016 at 05:00 point

I'd love to see a link to the actual instruction set (the picture on the main web site is very limited... e.g. what are the condition codes?) and the core block diagram (there is a very fuzzy picture in your blog of it which I can't read) and there is talk of a web simulator, but I can't find that either. 

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Yann Guidon / YGDES wrote 08/07/2016 at 05:09 point

Wel this is weird since I do my best to keep the data easy to find and use. I'm online now, come chat with me !

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zuul wrote 01/20/2016 at 05:48 point

cool keys

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Yann Guidon / YGDES wrote 01/20/2016 at 22:58 point

Thanks !

You can read more about them in the comments of the video

as well as there https://hackaday.io/project/8121-discrete-yasep/log/27062-keyboard-proof-of-concept

I know that cool keys are important, but these are not ideal. They come from very old surplus (long disappeared) and I want to create a design that can be replicated at will and as cheap as possible... Any help is welcome :-)

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euchcat wrote 10/26/2015 at 21:50 point

Great!
What memories coming back ...
I learned on a computer LPTF1 circuit (or a similar name) with a 6502 microprocessor ...

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Yann Guidon / YGDES wrote 10/26/2015 at 22:50 point

Glad to bring these memories back ! I can't imagine how hard it was to "pump" back in these days... (Shadock reference ;-) ) Today it seems quite easy to me to design this computer, I am spoiled by the luxury of dirt-cheap parts and access to worldwide stocks of parts that I never heard of before...
Oh and not being tied to the scarce pocket money of a teenager is another amazing thing ;-)

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euchcat wrote 10/27/2015 at 18:09 point

Yes, for me too, yesterday the existing tools for designing were with an enormous cost, and now we have an great choice of performing tools for that , cool ! :)

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Yann Guidon / YGDES wrote 10/27/2015 at 18:40 point

My tools of choice remain pens and paper. When my free brain works :-P

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Andrew Starr wrote 10/20/2015 at 03:08 point

Great! How soon until it's running a T-1 emulator?

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Yann Guidon / YGDES wrote 10/20/2015 at 12:37 point

At the current pace, a couple of years. Or a decade, who knows ? It's not a critical project for me, but I decided that 2016 will be the coolest and the most fun year! (until 2017 at least).

A T-1 emulator requires a complete and accurate architecture definition and good documentation so it will be more work for you. I'm sorry. However you can then write your own emulator in a high level language (hopefully in JavaScript so you can reuse all the bells and whistles of the #YGWM Whygee's JavaScript Window Manager  )

Once your high level code works, it can be ported and rewritten in #YASEP Yet Another Small Embedded Processor assembly language. The good news now is that the YASEP is Mandelbrot-complete, at least its 2013 version (2014 has been broken and it will take a lot of time to repair)

So it will take "a while" to run a T-1 emulator on this machine but there are very useful tools that will speed up the design and you can already write and simulate code. How fun do you think it is to run JavaScript code in your browser, simulating a processor that emulates a stack machine ?

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