This log is both an introduction and a "note for later" about the scheduling of the control signals.
The Discrete YASEP is derived from the microYASEP but due to technology differences, the scheduling can't be reused as is. The microYASEP uses DFF latches, which make it a fully synchronous design (alternating layers of DFF and logic that can be pipelined). However the Discrete YASEP uses 74HC193 up-down counters for the registers, their behaviour for the preload timing makes them look like transparent latches.
Because of this (and other architectural factors), the operands are latched in the input of the ALU. This prevents data from looping or become unstable in the case where a register is both a destination and source for a computation.
This makes the design a 2-cycles system:
- the first cycle fetches the operands from the registers (or memory) to be latched in the ALU
- the second cycle computes the operation then latches the result(s) (if the condition is evaluated as true) in the destination register (and might update others as well).
Each cycle has sub-cycles as well. The sequencer needs a higher clock input frequency, at least a four-phases clock where the phase 1 latches the operands and phase 3 latches the results, but it's more complex than that because both cycles have a different latency and the scheduling changes a bit between short and long instructions (due to the long immediate operand).
(to be continued)