There is a tie between the 24.576MHz and 18.432MHz source frequencies.

The higher the frequency, the better resolution for scheduling the sub-cycles of each instruction. Finer sub-step allow a faster execution.

24.576MHz allows 40.7ns steps, but it is not as handy as 18.432MHz to derive "useful" frequencies, for serial communication for example.

I have ample supplies of both frequencies. 24.576MHz is desired but how can I extract the 3.6864MHz that is used by the other circuits ?

24.576/3.6864 = 6.6666....

Actually it means : for every 20 cycles at 24.576MHz, there are 3 cycles at 3.6864.

You can substitute "transition" for "cycle" and it becomes pretty interesting, from a logic circuit perspective. A 74HC4017, a 74HC74 and some AND/OR gates will do the trick.

First, the 4017 will turn on one output every 10 cycles. One cycle is 2 transitions, right ? So one 4017 can work with 20 transitions. Each transition can be identified with a AND gate between the 4017 output and the clock signal (inverted if necessary).

One can evenly divide 20 by 3 with the intervals 7, 7 and 6. 3 AND gates are used to combine the 4017 outputs with the (inverted?) clock signal. The result is ORed and privides 3 pulses every 10 cycles.

The pulses clock a 74HC74 with the /Q output looped back to the D input, which makes a cleaner 3.6864MHz signal (with some jitter).

Did I mention that I love the 4017 ? :-)

This circuit is rather easy to build with discrete parts but I might have to use a CPLD or tiny FPGA for the sequencing logic, because the timing gets pretty critical. I wish I could reach 4MIPS, that's 6 sub-cycles @24MHz and only 4 @18MHz

Another interesting property of 24.576MHz is that it is a multiple of 2^16 (3×125×65536) and it's handier for power-of-two real-time scheduling (more on this later). OTOH 18.432MHz is "only" 16384×1125.

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