The precedent log had a few flaws that I will correct here ;-)

The main flaw was to try to design the logic "in my head" so here is the detailed "equation" for one level of shift, considering an hypothetical 4-bits input, with bits named A, B, C and D (it would still work with only A, B and C but I'm feeling generous).

From there, the circuit is straight-forward to draw:

Repeat and expand: 16 bits instead of 4 in length, and 4 layers instead of just one.

The adjustment logic on both sides will grow in depth, from 1 bit in layer 0, to 2 bits in layer 1, 4 bits in layer 2 and 8 bits (one half on each side) for the last layer. This is where we see the advantage of the integrated AND gate included in each '153 as it adds no overhead :-)

Some overhead is in the decoding and control logic, that is not completely represented here. The /Right/Left signal would ideally be directly coming from the instruction word, if it was better organised, so here is a new attempt:

• Left/right are one half each of the instruction group.
• There are 3 left operations and 4 right operations so the BSWAP operation is tucked in the left operations
• There are 2 shift operations per direction (with and without OR), plus one rotation. The remaining is either arithmetic shift (SAR) or BSWAP which should have the same position in their respective group (let's say the 3rd so they are easy to decode).

The instruction bits are allocated in the SHL group:

• bit 2: direction (0: right, 1: left)
• bit 1: Shift/rotate (0: shift, 1: rotate or special op)
• bit 0: OR or special op when 1

The opcode can easily be decoded with a simple 74HC138 or '238, depending on the needed signal polarity, and (N)AND gates do the rest in the circuit.

The codes are thus derived:

• 0 : SHR
• 1 : SHRO
• 2 : ROR
• 3 : SAR
• 4 : SHL
• 5 : SHLO
• 6 : ROL
• 7 : BSWAP

In the case of BSWAP, the SI4 operand MUST be 0 and the decoding logic will do the swap at the last layer.

I think I like this design :-)