Custom 8-bit CPU and Computer (on an Arduino)

A custom 8-bit CPU designed in Logisim, then on PC as a VM, then in hardware using an Arduino as a host.

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My objective is to build a very simple 8-bit computer, with a custom CPU instruction set. It will be designed in Logisim, tools and/or a VM written for Windows/Linux. Finally, hardware implementation will be done on the cheap by using an Arduino.

Some Background:

I kind of missed the Altair/IMSAI/Cosmac era of early personal computers, I got my first machine in about 1980/81 and ended up owning machines from most of the popular manufacturers that were marketed in the UK (Commodore, Sinclair, Atari, Tandy etc).  Still, my favorite was a 'Science Fair Microcomputer Trainer' kit from our local Tandy store. Little more than a TMS-1000 microprocessor and some LEDs and a hex keypad, I learned so much from it.  Over the years I broke it and was never able to find another similar substitute.   This project is heavily inspired by that TMS computer kit.

I'm not much of a coder, I'd not written anything since the 90's, but I taught myself Lua, then Javascript and HTML5 and finally Python.  I used these to create software CPU's and little test programs to run on them.  I created this project page in 2015 and implemented a few proofs of concept on an Arduino.  Eventually other things got in the way and the project stalled.

Recently (Oct 2017), I became aware I had a limited understanding of what was going on at a lower level in a CPU, how the instruction set was related to the underlying hardware.  For example how the instruction decoder could trigger control lines and how the registers and ALU were connected, beyond a very superficial level.  I became aware of some free software called Logisim and decided to renew my project by designing my CPU and computer from a 'simulated' lower level.

Current Project Objectives:

  • The computer and 8-bit CPU will be designed in Logisim.
  • Tools and/or a VM will be created for PC (Linux/Windows).
  • The CPU will be implemented in hardware using an Arduino 'host', cased as a standalone computer.

  • Final (I think) Design - Jan 26, 2018

    Martian01/26/2018 at 01:23 0 comments

    I think this is the 'final' design:

    All I've done is moved the instruction decoder, branch test etc upwards - basically so the whole design fits nicely on my laptop screen while running.  Any faults I'm finding are in the 12bit microcode, where I made some entry mistakes and other silly mistakes, but I'm finding and killing those quickly.  I can REALLY appreciate the microcoded CPU concept now!!

    I think the CPU design stage is approaching the end.  Next would be the computer itself generally, devices etc.

    I know Logisim allows the manual loading and saving of RAM and ROM contents, that's ok to a point.  But I was wondering about making a simple OS, but I do not know if I could simulate a disk drive in Logisim.  IF ANYONE HAS ANY IDEAS, PLEASE LET ME KNOW.

    Beyond that, I guess I'll begin writing a console based emulator for Windows and Linux.  My plan is an integrated CPU VM or emulator, with file/program loading and saving and a machine code/assembler editor of sorts, all driven from a central menu.

  • Current Design - Jan 22, 2018

    Martian01/22/2018 at 23:08 0 comments

    I've added some labels etc.  Any questions, feel free to ask.

  • Update - Jan 21st, 2018 - First Rough Assembler

    Martian01/21/2018 at 02:11 0 comments

    After quickly tiring of working every potential program out in hexadecimal for the processor, I thought I'd be a clever git and write an assembler.

    In my head it seemed oh so simple, in reality it was like pulling my own teeth out.  I had no clue where to begin, any pointers I could find online ended up looking so convoluted, I'd fall asleep trying to read it all.  So, it's taken a month or so of guessing, second guessing, swearing like a drunken sailor and starting again.  Producing, the most vile kludge of code ever conceived by man in the name of programming, written in Python, it would make a Pythonista cry with shame.

    Anyway, it ain't pretty but it does the job. Of reading "in.asm" and writing "out.hex", it formats the input assember, creates a table of labels and constants, does a bit of magic and converts the result out as a stream of hex values, it's VERY unforgiving of mistakes.  This can be copied and pasted directly into the RAM or ROM of Logisim.

    I dare say I will keep returning to it, refactoring the awful code, but for now, it kind of works.

  • Current Instruction Set - 23rd Dec 2017

    Martian12/23/2017 at 02:40 1 comment

    00	hlt
    01	hcf
    10	ldw r0, $addr
    14	ldw r1, $addr
    18	ldw r2, $addr
    1C	ldw r3, $addr
    11	stw r0, $addr
    15	stw r1, $addr
    19	stw r2, $addr
    1D	stw r3, $addr
    20	inp r0
    24	inp r1
    28	inp r2
    2C	inp r3
    21	out r0
    25	out r1
    29	out r2
    2D	out r3
    30	brz r0, $addr
    34	brz r1, $addr
    38	brz r2, $addr
    3C	brz r3, $addr
    31	bnz r0, $addr
    35	bnz r1, $addr
    39	bnz r2, $addr
    3D	bnz r3, $addr
    32	bgz r0, $addr
    36	bgz r1, $addr
    3A	bgz r2, $addr
    3E	bgz r3, $addr
    33	blz r0, $addr
    37	blz r1, $addr
    3B	blz r2, $addr
    3F	blz r3, $addr
    40	mov r0, r0
    41	mov r0, r1
    42	mov r0, r2
    43	mov r0, r3
    44	mov r1, r0
    45	mov r1, r1
    46	mov r1, r2
    47	mov r1, r3
    48	mov r2, r0
    49	mov r2, r1
    4A	mov r2, r2
    4B	mov r2, r3
    4C	mov r3, r0
    4D	mov r3, r1
    4E	mov r3, r2
    4F	mov r3, r3
    7F	jmp $addr
    80	add r0, r0
    81	add r0, r1
    82	add r0, r2
    83	add r0, r3
    84	add r1, r0
    85	add r1, r1
    86	add r1, r2
    87	add r1, r3
    88	add r2, r0
    89	add r2, r1
    8A	add r2, r2
    8B	add r2, r3
    8C	add r3, r0
    8D	add r3, r1
    8E	add r3, r2
    8F	add r3, r3
    90	sub r0, r0
    91	sub r0, r1
    92	sub r0, r2
    93	sub r0, r3
    94	sub r1, r0
    95	sub r1, r1
    96	sub r1, r2
    97	sub r1, r3
    98	sub r2, r0
    99	sub r2, r1
    9A	sub r2, r2
    9B	sub r2, r3
    9C	sub r3, r0
    9D	sub r3, r1
    9E	sub r3, r2
    9F	sub r3, r3
    A0	and r0, r0
    A1	and r0, r1
    A2	and r0, r2
    A3	and r0, r3
    A4	and r1, r0
    A5	and r1, r1
    A6	and r1, r2
    A7	and r1, r3
    A8	and r2, r0
    A9	and r2, r1
    AA	and r2, r2
    AB	and r2, r3
    AC	and r3, r0
    AD	and r3, r1
    AE	and r3, r2
    AF	and r3, r3
    B0	or r0, r0
    B1	or r0, r1
    B2	or r0, r2
    B3	or r0, r3
    B4	or r1, r0
    B5	or r1, r1
    B6	or r1, r2
    B7	or r1, r3
    B8	or r2, r0
    B9	or r2, r1
    BA	or r2, r2
    BB	or r2, r3
    BC	or r3, r0
    BD	or r3, r1
    BE	or r3, r2
    BF	or r3, r3
    C0	not r0
    C4	not r1
    C8	not r2
    CC	not r3
    D0	xor r0, r0
    D1	xor r0, r1
    D2	xor r0, r2
    D3	xor r0, r3
    D4	xor r1, r0
    D5	xor r1, r1
    D6	xor r1, r2
    D7	xor r1, r3
    D8	xor r2, r0
    D9	xor r2, r1
    DA	xor r2, r2
    DB	xor r2, r3
    DC	xor r3, r0
    DD	xor r3, r1
    DE	xor r3, r2
    DF	xor r3, r3
    E0	lsh r0
    E4	lsh r1
    E8	lsh r2
    EC	lsh r3
    F0	rsh r0
    F4	rsh r1
    F8	rsh r2
    FC	rsh r3

  • Current Design - 21st December 2017

    Martian12/21/2017 at 21:36 0 comments

    This is the current design I'm working with:

    [image removed]

  • Update - December 2017

    Martian12/20/2017 at 03:39 0 comments

    Firstly, I have to acknowledge I learned so much from the following site:

    ..and the book "But How Do It Know? - The Basic Principles of Computers for Everyone"

    I had come up with a design, featuring ideas I'd learned and some part's I kludged together myself.  I did post it here - briefly!  But it wasn't perfect, and as I worked with it, I realised there were some fundamental problems with it and limitations.  I'd really compromised the ALU functionality by reducing the number of ops down to four.  The decoder was my own attempt from scratch and it was a mess.

    So scrapped it and re-implemented it, mostly during late November/early December 2017. 

    It's still a 8-bit CPU with a 16-bit Address bus.  The Address Register is comprised of two 8-bit registers.  There are still four general purpose registers.  Now the ALU has 8 operations (adder, subtract, AND, OR, NOT, XOR and logical shifts left and right) and produces values for the Negative and Zero flags.  The decoder is greatly simplified and features a 4K ROM with 12-bit microcodes.

    I will upload some Logisim diagrams.

    Currently, I am TRYING to write an assembler.  I cobbled together some Python to open a file and do the magic, I thought I had it worked out, when I tried some other test programs I found lots of problems.  The code is a mess, so I think I will write another from scratch - sometimes, as I've found with the CPU design, the best thing rather than patch a lost cause is to ditch it and start again, hopefully having learned something before.

    That will probably be the focus of my time over the holiday period.

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Hacker404 wrote 09/20/2017 at 09:20 point

Who could resist a computer that had Bacon Lettuce and Tomato (BLT) :)

I haven't used Logisim but just looking at it, I would like to mention that most FPGA/CPLD IDE environments have schematic entry which is very much like what I see of Logisim. Schematic entry isn't very practical for large FPGAs but it's a good start to get used to the IDE. If you are going to try this then I recommend starting with Altera Quartus as it's easy to install and it's easy to find cheap CPLD breakouts with programmers cheep on ebay. Just use ebay to search for Altera CPLD and look for kits with a programmer.

  Are you sure? yes | no

Martian wrote 09/20/2017 at 21:09 point

Hi, thanks for the info.   I've not really much first-hand experience with FPGA, I worked for an optical networking firm that designed chips (on Xilinx?) about 15 years ago with Sun workstations, but I was busy running their UNIX network and never got to explore it properly.  I've only seen a few development boards in the past and they were a bit out of my price range (which is next to zero).  Arduino's have become a bit of a pooman's alternative for me to create stuff and flash it over.  I appreciate the info, I'll look into that Altera CPLD kit and read up on what's involved.

  Are you sure? yes | no

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