UPDATE V: Here's a demo using a TTL input as an example of my original "weird circuit" in use
Note that by varying the input-voltage to greater than about 3.65V, the circuit's very similar to mine, current flows from the base through the collector. And at nearly 5V, current flows into the NPN's emitter.
UPDATE IV: I FOUND A USE for the weird PNP mistake!
UPDATE III: Found a REALLY HANDY REAL-TIME-ish SIMULATOR
and more simulation-links at the bottom.
UPDATE II: New Interesting circuit, at the bottom.
UPDATE: ROTFL, it's just diodes... more at the bottom.
Over at #Improbable Secret Project, (Log: https://hackaday.io/project/18868/log/50780-open-collector-fail-the-atx-power-switch-saga-continues) I accidentally discovered that the following circuit is possible:
The key-factors are:
- Transistors work similarly when C and E are reversed (though with tremendously lower current-gain)
- TTL ... nah, that isn't really relevant, after all.
So, what we have, here, is a *buffer*, rather than an inverter, as it would be with the NPN I'd intended to use.
It's sort of an emitter-follower, except using the "key-factor" this makes it more of a "collector-follower."
(BUT, allegedly that term is reserved for another purpose.)
Note that when the input voltage is greater than (V+ - 0.6V) (high, assuming VBC-on=0.6V), the transistor is *off*.
When the input is less than (V+ - 0.6V) the transistor is
*on*, and the output-voltage follows the input voltage... So, a 0V
input would result in a 0.6V output (which is lower than a TTL circuit's VIL-max of 0.8V, nice) so it will be Low.
a TTL circuit's VIH-min is something like 2.0V, and obviously VOH-min
must be greater than that. So, feeding 2.0V into the input,
the transistor will be on, but its output-voltage will be 2.6V... High.
(Of course, these depend a little bit on the value of the base-resistor)
Well, here's an interesting result...
This is an AND gate, I think!
I'm calling it a [L]AND gate, because, without the pull-up resistor, it's an AND which only outputs the Low state, the "high" state is determined by the load (the pull-up resistor, in this case).
Similarly, if I've got my logic right, the opposite (using NPNs connected to V+), creates a [H]OR gate.
I'll stick to discussing the [L]AND gate...
When both inputs are the same, we have the same effect as with a single transistor... That takes care of the 00, and 11 states of an AND gate.
What when one input is "high" and the other is "low"?
My THEORY (untested) is that the lower of the two inputs will be followed.
The reality may be significantly different... Since the current-gain is really low (like IC=2*IB), and since the high input would imply a higher current going into that transistor's base, that transistor (the one pulled high) will have a greater IC... and this is where I can't quite wrap my head around it... because a higher IC (through B) would create a greater current through C->E, which would cause it to pull even lower. Hmmm...
So, I think it's an AND gate, but I'm not certain.
This came as a result of analyzing @Ted Yapo's circuit from #CBJT Logic:
Note the normally-biased PNPs Q9 and Q10 in that circuit form a NAND gate. Which seems a bit backwards, since they're in parallel. But if the other transistors were removed and replaced with a pull-down resistor (and if this were 5V logic), then we'd have essentially the exact opposite of the [L]AND gate... they'd be a [H]NAND gate.
Now, I find it a bit strange that two *parallel* transistors could create an AND (or NAND) gate... OR, sure. NOR, sure... So I took a bit to think about it and, here's my conclusion. NAND is actually the same as an OR which has its inputs inverted.
| OR >---
| NAND |o--
Unfortunately, it doesn't seem [to me] too simple to interface a [L]AND and [H]NAND gate such that the series transistors (and pull-resistors) could be removed... but I could be mistaken....
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