ECL or CTL : what's the fastest topology for discrete gates ? [updated]

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yann-guidon-ygdesYann Guidon / YGDES 06/14/2018 at 06:4420 Comments

EDIT 20180918 : Please see the erratum/confession at the bottom !

Private discussions and readings (books, online etc.) bring a very important question : what's the fastest gate for discrete circuits ?

ECL is notoriously fast. @Dana Myersrecently played with it and reached about 0,5ns propagation time in inverters in a ring oscillator, on a breadboard and with a fistful of MPSH10.

(note : the ideal current is about 4mA per gate and the oscillator reaches 307MHz on breadboard)

On the other hand, Complementary Transistor Logic is a bit like DTL but the input diode is replaced by a PNP. This greatly increases the input impedance and helps with many things. Operating voltage and current might be significantly lower, it even reduces the transistors count by 2 compared to ECL. But if it's easy to get one sort of FAST transistors, the complementary type might not be easy, as cheap or as fast... I have only stocked one type of germanium (PNP, because Ge NPN is rare) and silicon (well, I have mostly NPN, some PNP but i have no idea how to find a PNP equivalent of BFS480...

(as usual, the 2 diodes in series could be replaced by a red LED ?)

The BC857 has a high gain so the input current can be very low and this reduces fanin/fanout issues. The speedup capacitor might need some tuning, maybe 1 or 2nF ? And the resistors could be reduced to increase current and speed.

I've also read mentions of hysteresis of CTL gates, due maybe to capacitance, which can reduce the operating speed. A Schottky diode might be needed to remove bias buildup... or even add a resistor in parallel with the speedup capacitor ? Or what about simply avoiding the voltage shift by using more power rails ?

Another parameter is : sometimes, using better and faster transistors simply lets the gate run faster. But it can come at a high price so topology is still critical...

Now, the only way to compare is to try, right ?

(repost courtesy of @Dana Myers )
Just for the sake of discussion, Fairchild had their own TTL family back in the day when the 74-series was not an industry standard (or Fairchild had their "74F" series). They did TR, TD and TT : transistor-resistor logic, transistor-diode logic and here transistor-transistor logic. The datasheet shows no Baker clamp, but R5 might have helped...

But 5 transistors for one NAND, that's similar to ECL density :-D

EDIT 20180918 : Mea Culpa !

Apparently I made a big mistake and used the wrong schematic for CTL.
CTL seems to be derived from ECL and is claimed to be even faster (for certain values of "fast" because I still have to try it)

From what I have gathered from the MT15 project, with BC847\BC857:

The schematic is subtly different from the one I included earlier :

As above, the inputs are PNPs that short the base node to GND. However the difference with the previous schematic is the output stage: it is a follower and not a "shorter to GND", so it does not saturate.

Note also that the gate above is a AND gate and no inversion takes place. I'd love to see an inverter, a MUX, a OR, a XOR...

I'm also unsure about the logic levels, temperature susceptibility and noise : I'll have to compare to ECL and DCTL :-P

The availability of a richer set of logic functions is critical for me, but there is an added simplicity to CTL : one can use SIL resistor networks to keep the parts count low and share a single package for several gates. No caps, no diodes, only 2 resistors with very close values...


Ken KD5ZXG wrote 12/09/2021 at 17:18 point

Perhaps flip those rails. Variable ON following may be an easier task for PNP than ON/OFF switching. That circuit has unity gain or less. At some point, it will need an extra stage to square it.

  Are you sure? yes | no

Dylan Brophy wrote 06/19/2018 at 19:24 point

It would be a cool challenge to make an ECL computer instead of a TTL computer.  I am curious to see how fast it could be clocked ;D

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Yann Guidon / YGDES wrote 06/19/2018 at 20:41 point

That's why I stocked about 8K BFS480 (16K transistors) last year :-P

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Dylan Brophy wrote 06/19/2018 at 22:14 point

Geez!! So many!! Thats more transistors than the total number of electronic components I have!!

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Yann Guidon / YGDES wrote 06/19/2018 at 22:28 point

Dylan : in SC70-6 (SOT363) that's only 3 standard reels :D

and it takes much less room and weight than the almost 20K BC559C in a box, for the "prototype" :-P

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Ken KD5ZXG wrote 12/09/2021 at 17:26 point

I nabbed a bag of 5000 gold doped KSP10's for penny apiece when Arrow closed out that part. Or maybe was the Schottkys I got the deal on. Something was 5000...

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Yann Guidon / YGDES wrote 12/10/2021 at 15:25 point

@Ken KD5ZXG one can't have too many transistors, right ? ...

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K.C. Lee wrote 06/19/2018 at 20:53 point

Cray I is ECL at 75MHz.  May be Yann would stock even more transistors?

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Yann Guidon / YGDES wrote 06/19/2018 at 22:30 point

75 ? not 80 ?

I'm not sure I could reach such a high speed, but the size/scale is clearly out of my range :-P

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K.C. Lee wrote 06/20/2018 at 00:00 point

You are right. It is 80Mhz. Must have mixed that up with 75MHz Pentium.

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Julian wrote 06/20/2018 at 10:37 point

The Cray I was based on ICs, though.  Perhaps you're thinking of the CDC8600, which was ECL based on discrete transistors (or would have been had it ever been finished)?

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agp.cooper wrote 06/17/2018 at 13:10 point

I have tried LEDs and they work okay (did not find then much slower), but for the input diodes I would stay with the 1N4148 or the BAT81 etc. The a 1nF speed capacitor was about right for my work but was less important (can be omitted) when the bias resistors are just right.


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agp.cooper wrote 06/17/2018 at 13:04 point

Simulation of DTL does not work too well. So not surprised. The trick is to bias the transistor so that when the output is high, the output voltage is not 5v but something like 4.5v. I use the 2N3904 as they as common and faster than the BC548.


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K.C. Lee wrote 06/15/2018 at 05:21 point

Your speedup cap don't need to be too much bigger than the Miller capacitance of the transistor you are driving.

>(as usual, the 2 diodes in series could be replaced by a red LED ?)

LED have larger parasitic capacitance than signal diodes.  Larger junctions vs something optimized for switching and shorter recovery time.

This is also why one should not use *rectifiers* as switching diodes. 

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Yann Guidon / YGDES wrote 06/15/2018 at 05:34 point

So yes, these diodes are a problem... level shifting is the root cause here.

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K.C. Lee wrote 06/15/2018 at 18:10 point

The 390R and the 820R already forms a voltage divider in the absence of diodes//cap.  This means you don't need a new supply or level shifting (i.e. get rids of the diodes and cap).  

Play with the value of 820R (reduce it) such that the voltage swing (when the input stages are on/off) are what you want.  A reduced swing at the BC557 also reduces the rise/fall time.  :)

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Yann Guidon / YGDES wrote 06/15/2018 at 18:14 point

hmmmm you must be on to something here :-)

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agp.cooper wrote 06/17/2018 at 13:16 point

The idea behind the "two diodes" is to increase the DTL noise immunity.

In my mind they are essential!

I also did not have success with the Baker Clamp but YMMV.


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agp.cooper wrote 06/15/2018 at 02:51 point

The big difference between the two options is speed. You can get down to about 50ns with the DTL (without using special transistors). That is 100 times slower than the ECL quoted above.
DTL is however TTL compatible. has a version that uses less components is faster (but not as fast a ECL), but it has less noise immunity.


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Yann Guidon / YGDES wrote 06/15/2018 at 04:57 point

Thanks for the link Alan :-) I forgot about this page... but it's very useful for another project I have :-)

In the picture I have shown, the BC557s replace the input Schottky diodes, it's one significant improvement. I tried to study the gate but it doesn't work well for me on paper, I should probably try on breadboard. A Schottky Baker clamp is crearly missing of course. But it's the "level shifting" in the middle that confuses my brain... and I'd rather have a topology with only one type of NPN (like in ECL) :-)

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