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The rule of 50 (or so)

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Yann Guidon / YGDESYann Guidon / YGDES 09/10/2018 at 12:2710 Comments

[updated 20180930, read the comments below for more background]

People usually confuse the operating frequency of the computer with the max. frequency of its individual parts.

Let's say a CPU runs at 1GHz, that must mean each transistor switches 1 billion times per second, right ? Hahaha I'm kidding.

Actually the Ft (transition frequency) of transistors is way higher than that. And the whole circuit is slowed down by other factors such as wires, capacitances, resistances that make distributed RC networks along with the capacitances, and countless other factors. Of course, the CDP (critical datapath) length matters too.

But in average, I have observed a 1:50 ratio between the operating frequency of a processor versus the "speed" of the constituting transistors, for reasonable architectures. This might be lower for recent ultrapipelined processors but when you make your own discrete processor, divide the Ft by 50 to get your final processor's speed. A ratio of 100 is much more realistic for a hobby project but it's less optimistic...

The ratio of 50 is a realistic ceiling that shows the influence of parameters outside the transistor's ideal characteristic. One such influence is the type of logic gate (TTL, DTL, CTL, DCTL, ECL...) so you have to measure your individual inverter gate speed (for example with a ring oscillator) for a better estimate.

I'd be happy to get more datapoints from various architectures and implementations. A chart would help us identify the factors that inflate or decrease this ratio and give us a better prediction.

Note : this rule applies to transistors and semiconductors, not relays, where the delay is limited essentially by the contact switching speed and RC delays are irrelevant.

Discussions

Ed S wrote 09/30/2018 at 10:59 point

There's a term of art for counting the logic depth of each pipeline stage in your microarchitecture, but I can't remember it! It will be related to your ratio. There is another term of art, which accounts for number of fanout-4-gates in a pipeline stage. See for example

The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays

http://www.eecs.harvard.edu/~dbrooks/cs246/deep-pipes.pdf

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Yann Guidon / YGDES wrote 09/30/2018 at 11:11 point

Yep I know FO4 :-) It's rather specific for integrated CMOS (and the "optimal" value varies with many factors), while we deal more with discrete circuits on Hackaday.
Discrete transistors are characterised by their "gain-bandwidth product" and this gives a max frequency when gain=1.
Of course my "rule of thumb" depends on many parameters as well, such as complexity of the device, width of the datapath, the type of logic gate and many other factors.

This is useful for a quick rough estimate of the "performance" of a computer given the transistor speed. For example : I have a bunch of 250MHz transistors, so the max clock I could hope to run is about 5MHz.

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Ed S wrote 09/30/2018 at 12:01 point

There must surely still be two parts to the delay through a combinatorial cloud: the transistor characteristic, and the logic depth?

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Yann Guidon / YGDES wrote 09/30/2018 at 12:31 point

yup but it's good to have a rough estimate, a rule of thumb, an order of magnitude so we can guess the maximum reasonable speed of the circuit :-)
It would be interesting to break that up, with small circuits, and going larger and larger...

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Yann Guidon / YGDES wrote 09/11/2018 at 14:16 point

Another datapoint : https://www.ecse.rpi.edu/frisc/theses/ErnestThesis/mernest-phdthesis.html

(I forgot which page tells about the relative frequencies but I remember it rekindled my interest with this ratio)

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Julian wrote 09/11/2018 at 10:33 point

If you want to collect datapoints, here's a good example for a heavily-pipelined processor: https://www.intel.com/content/dam/www/public/us/en/documents/research/2002-vol06-iss-2-intel-technology-journal.pdf gives a summary of early results from Intel's 130nm process, describing ring oscillators produced with the process as having 6ps/stage performance, and Pentium IV processors at 2.5GHz (which is less than the 3GHz they were aiming for).  Thats 1/67 ratio (or 1/33 for the small double-speed ALU the P4 used for simple instructions).  The 3GHz would have been right on the nose at 1/50.

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Yann Guidon / YGDES wrote 09/11/2018 at 13:26 point

Thank you !

yes, 50 is a bit high, but I chose a nice round number that is more optimistic than 100 :-)

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Julian wrote 09/11/2018 at 10:10 point

This one always used to annoy me, back in the day when slashdot was actually relevant (!) and they'd periodically put an article up describing how a new semiconductor process (usually some variant of SiGe) produced high Ft transistors and the general response was along the lines of "yeah! we'll all have 70GHz processors in the next 5 years!".  That got old very quickly.

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Yann Guidon / YGDES wrote 09/11/2018 at 13:24 point

That was also my feeling...

However I have never seen the "50 rule" laid out, discussed or even stated. I hope it's done now :-D

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Yann Guidon / YGDES wrote 09/30/2018 at 11:27 point

Meanwhile, Keysight uses InP for the front-end of their 110GHz scope.
https://www.youtube.com/watch?v=DXYje2B04xE

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