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Rationalisation

A project log for Trinity Core and Net

A 32 Bit Variable Length Instruction Set Core and Transputer Like Comms Network

Andre PowellAndre Powell 03/18/2019 at 22:590 Comments

As I think I mentioned I've taken the 'register file' payload memories and converted them into SRAMs. This meant I could have a crack at seeing how large a single Trinity Net came out as. The result was not great, ~51k Luts for a 3D node, which is about 43% of the present FPGA. Time to rationalise a few things.
I am not going to be able to get an FPGA large enough to go 3D but will be able to go 2D. With that aspect in mind I was able to get down to 8 connections and the area came down to 9250 Luts, this is a bit more feasable. Could get this happily into a single core system and have an array. Note that the internal interconnect has come down from ~17.7 k Luts, this coming down to 1.7 k Luts. Also note this is still more connections than the original Transputer as this had four, we have eight.

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