Now that they MPPA RTL with Block RAM has now been updated time it's time to start to see if it can be implemented in an FPGA.

This will be a stepped process.

First a single core with only one instantiation. This will be targetted at the first FPGA board.

Next to repeat the same targeting the larger FPGA.

After this two instantations in X.

The next stage will be a 2x2 array. I suspect that will be the limit.

After that I suspect having to save up or sell the family into white slavery.

It'll be quiet but I think bear up !