Scheduling the Grind

A project log for MagiLog: Open Automotive Datalogging

Developing a full featured datalogger on the cheap

nigelNigel 04/30/2018 at 00:040 Comments

For the last few weeks most of my time that I’ve spent on this project has been reading through textbooks for a Verilog refresher. While I’m making good progress through it some days I slack off completely and some days I go a bit too hard and end up burned out. So to ensure sustainable progress I’m going to whip up a dev schedule.

Currently there are three task groups that I can work on in parallel.

As a lot of the XMega code will depend on what I end up doing with the FPGA I’m going to somewhat ignore it for now and focus primarily on sim PBC design and the FPGA HDL. Here’s the schedule that I’m going to try to follow.


May 6

May 13

May 20

May 27


ADC Module

Analog PCB

Digital Module

IMU Module

Digital PCB


June 3

June 10

June 17

June 24


GPS Module


XMega Code Skeleton

FPGA Top Level Module

That’s all for now, I need to get back to the books.