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A project log for RPi WiFi

Fast RPi WiFi without USB

ajlittajlitt 12/12/2015 at 05:146 Comments

Submitted to OSHPark. Ignore the missing ground pins on the 2 headers, those are an artifact of the renderer.

I took a lot of wild guesses about the RF bits. We'll see if it actually works.

Highlights are an onboard 5V-3.3V LDO to keep from stressing the Pi's 3.3V regulator, pads for an FTDI-style UART header for the Pi's console UART, some stuff for debugging the ESP, onboard antenna, the usual U.FL / 0 ohm resistor setup for switching to an offboard antenna, and of course it's a Pi Zero sized HAT with a config EEPROM.

KiCad design files are on the Github on the main project page.


Marten Wikman wrote 12/26/2015 at 14:30 point

It's difficult to get a 50ohm co-planar waveguide using a 2-layer 1.6mm PCB. Width=0.5mm and gap=0.25 give more like 70 ohm on a 1.6mm PCB. Change antenna trace to width=0.7mm and  gap=0.154  and order 0.6mm PCBs from and you will get something very close to 50 ohm. See to get a rough idea of what is required to get 50 ohm impedance. 

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ajlitt wrote 12/26/2015 at 18:40 point

Thanks.  I had meant to switch the track to 1.1mm with a .18mm gap which should be much closer, but forgot before submitting.  The Sparkfun ESP boards are using a longer run of a similarly mismatched waveguide and the TI trace antenna, so I figure it should be good enough for a prototype.

Thanks for pointing out the thinner DirtyPCBs option, that's likely what I'll target on my next build.  I'll be trying to get rid of my not-so-mitered 90 degree turn by pushing the chip close enough to the antenna that there's nothing but the matching network in-between.

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Marten Wikman wrote 12/27/2015 at 09:02 point

Some other small things I found when checking the gerber files:

- The RF-reference path is interrupted by the +3V3 trace on the bottom layer. Route this trace on the other side of the chip and keep a complete GND reference under the whole RF-path. 

- Check if it possible to route the SDIO bus on one layer and have a complete GND plane under it. This will improve SI and reduce unwanted emissions from the SDIO bus.

- Move the via close to pin 3 and 4 downwards to improve the RF-reference path on the bottom layer. 

- If you check the datasheet for a u.fl connector (, page 3) you will see that there should be no copper  under the connector.

- I would add a 100nF capacitor  to every +3V3 pin on the chip. There is plenty of space on the bottom layer to add decoupling capacitors close to every +3V3 via. I have not found any ESP8266 design which does this but it is good engineering practice to add a decoupling capacitor to every power pin on a chip.

- There is no need to use thermal reliefs on any pad connected to GND. Use complete copper fill on every GND pad. Especially important on the matching network and u.fl connector.

- There is no via stitching next to the u.fl connector. You could also add a little more GND-GND vias everywhere on the board. 

- If you don't succeed with removing the 90 degree turn, try to change it  to a rounded corner.

- It looks like some of the RF-path stitching vias are violating the 0.25mm gap. Move these vias a little bit away from the RF-path if you will use 0.25mm gap on the next rev. 

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Alex wrote 12/12/2015 at 10:41 point

really nice. And another reason to try kicad4.
A nice idea would be also to add an i2s soundcard to this pcb. So you can fix the two major problems of the zero with only one hat.

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ajlitt wrote 12/12/2015 at 19:21 point

Did this one after upgrading to 4.0 stable.  I really like the interactive push and shove router.  Hopefully curved traces and impedance controlled miters will come in the future.

I like the idea of an I2S DAC.  There's plenty of room on this board.

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Craig Hissett wrote 12/12/2015 at 09:37 point

This is awesome - I cant wait to see assembled article when your boards arrive!

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