The digital logic input is the feature I was looking forward to, the most. A slot at the bottom right corner of the display allows for a logic analyzer type attachment that allows for 16 digital inputs, separated in 2 busses with a range of ±40V. All 16 channels can be displayed separately, controlled through a menu that can be brought up with the blue button to the left of the attachment slot. I like the marking on the button in best VHDL little endian fashion (D15 downto D0). Trace height and location on the screen can be easily adjusted to be optimal for visual and data analysis.
The advanced feature of the digital input port are 2 busses that can be configured as different bus types. Available options are parallel (up to 20 bits when the analog channels are included!), I2C, SPI, RS232/UART, CAN and LIN. The setup is very straight forward with the usual Tektronix menu structure. After selecting the bus type, all bus signal inputs need to be assigned to a channel which can always be one of the 16 digital logic inputs or one of the 4 analog channels. Thresholds, active levels and edges have to be set for proper capturing. Trace labels (pre-set names or custom entries) and bus data display (HEX, BIN, ASCII) help a lot for quick and easy analysis of captured data.
As my Arduino shield test board gives easy access to SPI and UART interface, I will focus on those, but operation will be very similar for other bus types.
With the bus set up as SPI, trigger options are chip select (SS or Slave Select in Tektronix terms) and the MOSI, MISO or both data signals with the option to trigger on one or more data words ( the # of bits per word can be set as well). After a capture is acquired, it takes several seconds for the bus trace to be computed and displayed, so patience is advisable. Especially as the analog trace show up instantly, I sometimes thought the bus signal was not captured but it always showed up after some time. In the image, the chip select (blue trace), MISO (yellow) and the decoded SPI bus purple are display. Green and red brackets show the transfer start and end, and hex numbers show the data words. Displaying the SPI clock signal would help to show the transferred bits, but once all the setup and hold timings are confirmed, a little trust into the capture system frees up some space on the display. An interesting observation is the faint ripple signal on the analog MISO line (yellow trace) at the 1st data word transfer. The digital capture of the MISO line shows a correct value 0x00, but the analog line reveals crosstalk between MISO and CLK. The MISO line is not driven at that point in time and points to a missing pull down resistor in the design. Lesson learnt: Even if the logic domain looks correct, it is always required to prove signal integrity in the time domain! On a side note, the SPI transfer shows the read out of the MAXIM MAX11300 Device ID register at address 0x00. The datasheet shows 0x0024 as ID value. The readout is 0x0424. Ooops, MAXIM.
The UART trigger is very similar, options are Tx or RX start bit, end of packet, data words or parity errors. The capture shows a Tx data byte 0x2D transfer after successful end of a previous SPI transfer. Trigger is set to the end of the packet, which turns out to be the middle of the stop bit. Here it would be easy to zoom in further with the really awesome wave inspector and look at the UART signal rise times or check the SPI data transfer. Triggering on UART events was possible without any issues, the problem an earlier reviewer had with this must have been fixed with updated firmware.
Another new (for me) feature is the event table, which is accessible through the vertical bus menu. It captures all events on the corresponding bus with a time stamp. Events are usually data words or bus erros, displayed in the same format as on the bus trace. Tables can be saved as a convenient .CSV file for further processing or documentation.