I'm returning to this project and made a few interesting improvements recently.  The first is that I cleaned up the verilog for the CPU core so that it could be built in Verilator, a pretty slick tool that takes a Verilog module and defines it as a C++ object.  You can then attach it to a test harness of your choosing to validate your work, check for regressions, etc.  Until now, I've been relying on tests on the FPGA systems themselves, and leaning heavily on the logic analyzer functions that Quartus provides to debug.  It works and is very powerful, but it's also quite slow and has limited flexibility.  This change, coupled with a new initialized RAM module allows me to compile and run arbitrary code pretty easily.

The main reason I went down this road is because I was planning to do a redesign of the CPU to support pipelining.  I've made some progress here as well, building a 5 stage pipeline that at least seems to move the proper data and signals around.

My challenge with pipelining in general is that most of the textbooks I've seen handwave over one of the most fundamental structural hazards - what to do when the instruction and data memory are on a common bus.  I decided to "solve" this problem by building the CPU core with two logical busses (data and instruction), and to marry them to a dual port RAM module.  Since the instruction bus will never do a write, this works well and will be sufficient to test out the pipelining.

I don't know how other designers solve this problem in the real world, but my plan is to link the CPU to an L1 cache, and have the cache layer deal with the vagaries of the "outside" bus.  This should also reduce the number of clock cycles required in each pipeline phase.  Right now my bus access logic requires two clock cycles minimum, but I think I could reduce this to one without too much effort.  I'm kind of working on the pipeline stuff one issue at a time, since I don't really have a good reference to crib from.  If anyone has any suggestions on something that's not crazy complex and would help give me some direction, leave them in the comments.