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Dummy's questions regarding CPLD

A project log for Very simple CPLD trainer

Very simple CPLD prototyping board, where .svf can be uploaded through USB! Total cost ($4) is comparable with Rasp Zero

kodera2tkodera2t 12/14/2015 at 09:327 Comments
CPLD is a programmable logic and NOT analogue component but when I think about logic component in 74 series, they are working for some exceptional operation. Here I confirmed two "exceptional" cases. These fact should be well known by experts but please enjoy it.

(Question 1) CPLD can organise RC oscillator?

Widely square wave generation is realised by 7404 or 7414 but is it possible by CPLD?

The answer is in the following movie..

(Question 2) CPLD can work as analogue amplifier??

It is well known that inverter in 7404 can work as analogue amplifier by putting proper feedback resistors. My question is, the inverter in CPLD can work as amplifier by proper resistor?

The answer was, NO! The inverting signal is generated by some "artificial" (I know it is not good word, but synthesized?) way, not by N and P channel complementary circuit and voltage feedback by resistor network does not work.

Have fun!

Discussions

esot.eric wrote 12/18/2015 at 05:02 point

Hah, I always wondered whether TTL could be used as an amplifier, and here you say it's "well known" ;)

Interesting experiments!

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Yann Guidon / YGDES wrote 12/14/2015 at 16:28 point

I think that you would have answers if you read the datasheets :-)

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K.C. Lee wrote 12/14/2015 at 12:24 point

Interesting experiment.  I used NS 16V8 GAL with resistor feedback (similar to CMOS inverters) as crystal oscillators a long time ago.

Is that using high power or low power setting for the macrocell?  Low power is not going to work as the cell is powered down between signal edges, so that breaks the feedback.

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kodera2t wrote 12/15/2015 at 11:46 point

it is not high power but also not low power. Default setting, which seems 20mA driving..

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K.C. Lee wrote 12/15/2015 at 13:02 point

What I meant was high speed under "Macrocell Power Setting".  (By default, "Macrocell Power Setting" is set to standard (Std), which is High speed.  This means that the macrocell is always on.  "Output Slew Rate" is set by default to "Fast" by default.)  I don't see any settings that need to be changed from default.

I am guessing that they might have a schmitt trigger (with a lot of gain from positive feedback) at the input that cleans up and speeds up the input signals.  That might prevent the part from being used as an amplifier.

Your observation are right, this part won't work as an amplifier.

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Xark wrote 12/14/2015 at 09:50 point

An interesting experiment.  I would think it would very much depend on the actual device topology, implementation technology and fabrication, but I am wondering if you saw this article where they managed to make a ring-oscillator in an FPGA (which changes frequency based on physical stress)? http://hackaday.com/2015/09/27/mystery-fpga-circuit-feels-the-pressure/

I wonder if this Verlog (or something like it) can fit in your CPLD? :-)

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kodera2t wrote 12/14/2015 at 10:13 point

I guess similar thing may happen! (I am not sure but depends on physical arrangement of chip in package, and relation of stress and distortion, which will make some permeability or some parameter change). Anyway extreme!

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