Register-Mapped Memory

A project log for F-CPU

The Freedom CPU project has a log here too now :-)

yann-guidon-ygdesYann Guidon / YGDES 02/22/2018 at 04:410 Comments

I just had this little "hah!" moment...

I keep thinking about how to make FC1 much more badass. While writing one of the latest logs of #PDP - Processor Design Principles  I realised I could/should have more than one data register per address register.

For example, 4 address registers are linked to one data register, and 4 other address registers are linked to 4 data registers each. Advantages include :

It looks like a weird mix between Itanium, SPARC and TMS9900... I have to ponder more about it but the overwhelming benefits are enticing.

I also have to find a proper behaviour for pointer aliases, should they trap ?