Capacitive LiPo Balancer

Using a switched capacitor network to shuttle charge between cells in a lithium ion battery while dissipating a minimal amount of energy.

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This is still in a very limited state, I haven't even drawn any schematics yet!

I would like to balance a 3s battery by just connecting a little board to its balance connector. 

A low power microcontroller (probably msp430) will be used to switch the capacitors and provide some feedback of when the balancing is done. A hibernation state will prevent overdrawing the battery. 

The whole thing could be done in analog, so I might go with that if the component count can stay pretty low. 

I expect to use mostly PMOS or PNP to switch between cells because driving NMOS could be tough. 

  • Possible building-block for my circuit

    Ross04/28/2014 at 17:41 0 comments

    LTC1043 - Dual Precision Instrumentation Switched Capacitor Building Block

    It looks like this chip, though not intended for my application, could be used. I would like to increase the capacitance over their example, but it should work alright. I'll hopefully get to try it out in LTspice in the next few days. Sadly, the current-carrying ability is pretty weak, because it's intended as a filter feeding a high-impedance (opamp) input. 

    It comes in a DIP-18 and SO-18 package, so great for prototyping and a future PCB. 

    There is even a micropower version, LTC6943, that has less convenient packaging for a prototype but lower bias current. 

  • Mosfet woes

    Ross04/28/2014 at 06:39 0 comments

    I started sketching out how to configure mosfets to perform the capacitor switching, and I ran into a body-diode problem. 

    First, I simply drew ideal switches. In position 1 (top position), C1 is connected to the top battery cell and C2 the middle cell. In position 2 (bottom position), C1 is connected to the middle cell and C2 the bottom cell. In this position, the two capacitors can be used to shuttle charge around the batteries. It could be done with only one capacitor and three positions, but having three states would be harder to implement that two states. Additionally, this should balance faster. A third capacitor shuttling charge between the top and bottom cells would also be good, but I am going to stick with two for a while. 

    Next, I drew the circuit using p-channel mosfets. I chose p-channel because they will be easier to drive from a low-voltage logic circuit or microcontroller. Simply have a pull-up resistor from the gate to the source to deactivate the transistor and then an open-collector/drain output to pull the gate to ground and activate the transistor. 

    However! this configuration poses a problem. In typical discrete transistors, the substrate is connected to the source. This causes an intrinsic 'body diode' that allows current to flow if it is forward biased. I have drawn in the body diodes of the top-right mosfet and bottom-left. If the top-left mosfet (S1) is allowing current to flow, it will try to bring the top of the capacitor up to 12V. The body diode of the top-right mosfet (S2) will allow current to flow up to its source, trying to clamp the voltage to ~8.7V. This would be a dealbreaker for using mosfets. 

    A solution is to connect the body or substrate of each mosfet to the highest potential in the circuit. This is common practice in IC design, but not usually available with discrete components. There are plenty of discrete parts available that could do this, but there might be a better solution using bipolar transistors. That will be a schematic for another day!

    I did a quick search for mosfet arrays that could be used to simplify layout/wiring on a circuit board and I found the ALD1107. It has four P-mos inside it, and it looks like all of the substrate connections are tied together and brought out to a pin. I could connect the substrate to the highest potential in my circuit and then forget about it. Sadly, this chip is not intended for power electronics of any kind. Rdson of 1800 Ohms and maximum Vgs/Vds of 12V. Does anyone know of a mosfet array chip with many pmos that could take a higher voltage? My digikey and mouser searches turned up dry.

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3DgeekStore wrote 04/10/2016 at 10:36 point

Relays are still there, can be a easy way to do

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mosaicmerc wrote 01/07/2015 at 13:38 point

Perhaps use a microcontroller with a hardware PWM capability to create a voltage multiplier boost to charge the capacitor. Then you can use optimized BISS switching bipolars to route the charge. That should amplify the charge moved per cycle and reduce the switching and hence lower switching losses. Also it compensates for any minor PN junction voltage drop.

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dave.m.mcdonough wrote 04/30/2014 at 14:57 point
I think you should spend some time on google looking into existing cell balance schemes. Here's the first few I picked off, didn't spend much time on it yet:

I would also review the control chip offerings from TI, IXYS, and IR. They make great products and it seems to me that something like this is a widespread enough issue that there should be a drop-in solution already available.

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Ross wrote 05/01/2014 at 20:34 point
Thanks for your interest Dave!

I have looked a little bit into commercial solutions, and I know that they will be able to do a more accurate job with less development time, but I am more interesting in the novelty of making something myself with a few parts and a PCB.

I am not aware of any capacitive balancer on the market. Almost all are resistive. I have seen a few inductive balancers, but making one of those would require more precision timing. With an inductive energy transfer, I would have to charge it from a high cell, disconnect it at the right time, and then connect it to a lower cell. Very little 'slop' would be allowed in the timing, and my switching times would have to be fast or with huge inductors. A capacitive balancer should just work slower when run at a lower frequency or with imbalanced timing.

Thanks for the tip on IXYS and IR. I haven't looked at IXYS and IR battery management, mostly Maxim and TI. I actually originally considered this project when using a TI Battery Protector chip a few years ago, and saw that it could communicate with a resistive balancer.

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