# V2 max speed test and V3 considerations

A project log for Discrete Binary to 7 Segment Display

Logic circuit to take a binary input and convert it to a 7 segment display

Part of the purpose of this project was to act as a testing ground for future projects made out of discrete logic. With this in mind I was curious to find out the max effective speed of the decoder. To test this I attached my function gen to the 8th's position on the input of Bit 3 depending on how you describe it. This produced a path 5 gates long untill the path reached the buffer or F segment driver for the display. I attached my scope to the gate of this transistor and simply feed increasingly high speed signals into it.

I observed some odd 50KHz oscillation on the positive portion of the signal when I drove it at 10Khz. It could be some sort of harmonic effect but the frequency of the noise seemed independent of the input frequency.

At 50KHz the wave form gets a bit nasty and I deem this the max effective frequency. Currently I am using NAND gates pulled high with a 10K resistor. I'm going to experiment with lower values and see if the max effective speed changes.

Now on to V3. I never planed to make a 3rd version but I might have a opportunity though my college to make a more educational version. I showed V2 to the professor who teaches the digital logic classes, a class I took and was able to apply to this project. She is interested in a though hole version that ideally will show the individual logic state of each gate. I thought of several ways to accomplish this but I settled on the most reliable option.

I'm simply attaching an LED buffer to each gate. This double the part count but with a board this size, (I esitmate 15-30 inches) I want it to work the first time!

On the left you have the old gate design and the right is the gate plus a buffer. For any one new these are simply 2N3904 BJT transistors.