Lately, I've been working on getting a JTAG for FPGA infrastructure up and running. 

The goal of this is two-fold:

• Simply learn to work with all the tools involved: RTL, OpenOCD, UrJTAG etc.
• Create some open source equivalents of tools that exist for Altera and Xilinx, but not for open source tool flows such as the one for Lattice FPGAs.

The first installment simply talks about a small JTAG controller GPIO block that can be used to replace Altera's In-System Source and Probes debug block.

The first article in the series can be found here.