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I hate DRAM!

A project log for T030

MC68030 based single board computer

Tobias RathjeTobias Rathje 05/15/2016 at 22:430 Comments

The time has come to add a lot more RAM. In order to boot a recent Linux kernel, I guess I need at least 8 MB and probably even 16 MB to be on the safe side.

32 AS6C4008's (or equivalent through hole SRAM) would require several additional boards and more importantly break the budget for this project.

So I have no other options than to dive into the wonders of dynamic RAM. After having tinkered with a DRAM extension board for a couple of weeks, I can certainly understand why a lot of hobbyists place these devices somewhere between "black magic" and "just not that easy to work with".

But now I have a 16 MB RAM board based on 4 x 4 MB 30 pin SIMM's which is stable most of the time...

I have implemented a DRAM controller in a second MAX 7128 CPLD. The controller is implemented as a FSM in VHDL and performs CAS before RAS refresh, address mux and data size decoding. I have never used VHDL before but a design example along with some sample code from an RD document from Lattice got me going in the right direction.

The DRAM controller code could use a cleanup and several wait states could probably be eliminated, but for now I consider it a huge success that it can pass a RAM test without crashing :-)

I have also added some more bypass capacitors to even out the current spikes that the DRAMs generate.

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