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A project log for Variable Precision CPU

A CPU without the restriction of a fixed data width

Paul SchmitzPaul Schmitz 03/22/2018 at 19:280 Comments

Warning: The following is a idea I had on how to do it. It is untested and most likely does not work like it should.

Here is a diagram to help understanding my explanation:

Except the subcounter register, which I will explain in the next paragraph, there is really nothing special here. There is a common bus, connected to the memory, ALU and a temporary register (or generally any number of fixed-width registers could be connected, which could be useful for output).

The main problem is, that you can't just build a ALU for adding two numbers, as the numbers may have any size. So what I added is a thing I called subcounter, which has 64 states, which each have 8 microinstructions, which can set the state of the subcounter. So one subcounter state can for example fetch the next two digits from a number from memory, add them together with the carry, store that at the output memory adress, determine whether all digits have been added (if yes: execute same subcounter state again; if not: load another subcounter adress which fetches the next instruction). This should allow the necessary recursion for the variable data size.

One thing I did not include in that diagram is everything related to conditional branching, as I am not sure how I will do that.

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