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• 22APR18: Schematic complete

  Stephen Newberry • 04/23/2018 at 03:12 • 0 comments

  I was hoping to have more done by now, but have been very busy. I managed to get a complete schematic uploaded under the "files" section here. There are 2 very minor outstanding items related to the schematic:

  • Pin-swapping will almost certainly change the FPGA pinout during layout
  • There are just a few components that don't meet my goal of having -40C to 85C temperature range. Those will be adjusted.

  A very messy BOM will be uploaded in a minute as well... Not quite complete but getting there!

  -Stephen

• 16APR18 Update, Power tree diagram added

  Stephen Newberry • 04/17/2018 at 03:47 • 0 comments

  As of today, a power tree diagram has been added detailing the power supply input protection, as well as the voltage regulation scheme. The schematic is probably around 80% complete, with the biggest outstanding item being the FTDI device. I'm hoping to be able to use the FTDI for multiple functions: JTAG to RISC-V MCU, SPI for configuration of the FPGA, a UART to the FPGA (if we need to connect to the RISC-V UART, we can just set up a pass-thru in the FPGA). I'm hoping that the SPI interface between the FTDI and the FPGA can be used as a data transfer port as well, after the FPGA has been configured. All of the IO pins to the FPGA have been assigned on the schematic, but I will go through the process of pin-swapping during layout. I don't think I'll make the deadline for schematic completion by the time the Hackaday prize entry date comes, but I will certainly continue to work on the project even after the deadline. I plan to release the design files to a public repository under an OSHW license once the design is complete as well.

  -Stephen

• 20MAR18 Update, Initial publication on hackaday.io

  Stephen Newberry • 03/21/2018 at 00:01 • 0 comments

  20MAR18:

  Original publish date on hackaday.io. At this point, the Artix-7 has been removed from the schematic, and the iCE40 has been added. Complete connection details on the iCE40 need to be added. Some component selection is still necessary (notably, what type of external memory to use on the FPGA). Additionally, the programming interface still needs design and validation.

  The fRISCy schematic is approximately 70% complete, and PCB layout is approximately 40% complete. Design documentation needs to be generated as well, including:

  • Updated system block diagram
  • Clock and Reset block diagram
  • Power distribution tree

  Upon completion of the schematic, the following files will be generated:

  • PDF of schematic
  • BOM
  • Component operating temperature range report

  Upon completion of the PCB layout, the following files will be generated:

  • Fabrication files:
    • Gerbers
    • Drill
    • Pick/place

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