16APR18 Update, Power tree diagram added

A project log for fRISCy: FPGA + RISC-V Digital Processing Board

fRISCy combines SiFive's new RISC-V microcontroller with a Lattice iCE40 FPGA for a platform that is all open source!

stephen-newberryStephen Newberry 04/17/2018 at 03:470 Comments

As of today, a power tree diagram has been added detailing the power supply input protection, as well as the voltage regulation scheme. The schematic is probably around 80% complete, with the biggest outstanding item being the FTDI device. I'm hoping to be able to use the FTDI for multiple functions: JTAG to RISC-V MCU, SPI for configuration of the FPGA, a UART to the FPGA (if we need to connect to the RISC-V UART, we can just set up a pass-thru in the FPGA). I'm hoping that the SPI interface between the FTDI and the FPGA can be used as a data transfer port as well, after the FPGA has been configured. All of the IO pins to the FPGA have been assigned on the schematic, but I will go through the process of pin-swapping during layout. I don't think I'll make the deadline for schematic completion by the time the Hackaday prize entry date comes, but I will certainly continue to work on the project even after the deadline. I plan to release the design files to a public repository under an OSHW license once the design is complete as well.