Jesús Arroyo Torrens
Icestudio is an experimental graphic editor for open FPGAs. It has been tested with iCEstick 1K and 8K boards in Linux 32, Linux 64, Mac and Windows.
It is built on top of icestorm project, that allows for first time to sintetize hardware into an FPGA using 100% open source code. Now it supports the whole iCEstick FPGAs family. Icestorm toolchain (icestorm, arachne-pnr, yosys) generates bitstreams from verilog code. Icestudio includes a JSON to verilog compiler that convert the graph diagrams (nodes and connectors) into verilog code.
Icestudio backend is called apio. This project, written in python, allows easy install, configuration and use of icestorm toolchain. Now it works on Linux x86, but more architectures will be supported in the future.
Icestudio frontend is based on nwjs (nodejs + js + html + css). Therefore, the frontend is fully desktop multiplatform, and it can be adapted to new devices (phones, tablets, etc.)
It is just the beginning. Do not hesitate to join this project!
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Icestudio
Experimental graphic editor for open FPGAs. Built on top of icestorm project.
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William Blankenship
simon
Lucas LucidVR
BetaMax
Hi, "_clk" is a label connected to FPGA pin 21 or J3 depending on the board. This clock works at 12 MHz. Also Ice40 boards can be configured for using PLLs: https://github.com/carlosgs/iceDAQ/tree/master/custom_pll.