37 Projects tagged with "Intel"

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Cornell ECE 5760 teaches FPGA design for DSP, video, and embedded control. Emphasis on parallel computing.

Teaching FPGA parallel computing

bruce-land Bruce Land

Giant Pacman with robots instead of sprites. Built by CREATE UNSW for Vivid Festival 2015

Real-World Pacman

Implement Edison mounted Flex Module that raises GPIO pins to 3.3V and both USB OTG and USB console.

Edison Host Flex Module

chris-hamilton Chris Hamilton

The 2015 Hackaday Prize

A compact IBM-PC compatible development board based on an Intel 80386SX CPU and an Altera Cyclone IV FPGA.

LSE-PC

pierre-surply Pierre Surply

Kernel & operating system for the Intel x86 platform written in C++ and Assembly https://github.com/maxdev1/ghost

Ghost Kernel

Home Automation and Monitoring System with many sensors and actuators to keep your home safe

ED-E: Home Automation and Monitoring System

A smart Helmet to keep you safe with luxury

Smart HuD - A Smart AR Helmet

The programming model I wish to use in ece5760 is LINUX running on the ARM processors, talking to hardware on Intel/Altera/Terasic board.

DE1-SoC CycloneV experiments

bruce-land Bruce Land

This is a derivative wikit program for you to control arduino 101 neuron A.I. function with simply drag and drop

wikitIDE: program arduino 101 visually

minqi-bao minqi bao

An Intel 8048 is used to generate a maze on a memory LCD.

8048 Maze Generator

A VGA driver on the FPGA side of the SoC connects to the ARM side. 8-bit pixels were used to conserve memory on the FPGA

VGA graphics for ARM SoC

bruce-land Bruce Land

Controlling large amounts of WS2812 LEDs with the Edison is as easy as writing it to an I2C Memory Array!

thingSoC NEOLED : NEOPixels on Intel Edison

pattern-agents Pattern Agents

The Cyclone5 DE1-SoC has a nice audio codec, with support on the Intel/Altera Avalon bus. An Avalon bus master does the DSP, and runs codec

Audio DSP on DE1-SoC

bruce-land Bruce Land

The DE1-SoC board supports NTSC/PAL input through a Video Input subsystem in Qsys. A camera is attached to the yellow composite video jack.

Video capture using DE1-SoC HPS

bruce-land Bruce Land

The memory systems of Altera Cyclone5 FPGAs have various features and limitations. I will not talk about the HPS here, only the FPGA.

Memory on Cyclone5 FPGA

bruce-land Bruce Land

This is a start at making a graphics coprocessor for the on-chip ARM9 cpu on Cyclone5 FPGA.

Fast FPGA Polygon processor for ARM

bruce-land Bruce Land

A FIFO between the Cyclone5 ARM9 and the the FPGA fabric is a convenient way to abstract away communication between them.

FIFO interface between ARM and FPGA on DE1-SoC

bruce-land Bruce Land

The "DE1-SoC University computer" IP which ships with the DE1-SoC is 320x240 resolution. This is a conversion and simplification to 640x480.

Cyclone5 VGA16-bit color ARM interface.

bruce-land Bruce Land

Let's run some code on the good old 4bit CPU.

Bringing alive Intel 4004

Run Windows 7 from a VHD on a NVME Drive

NVME Win7 VHD

stanislas-bertrand Stanislas Bertrand

The FPGA uses a custom floating point to implement integrators, and all the arithmetic necessary to solve ODE under ARM9 HPS control.

FPGA, Floating Point, differential equation solve

bruce-land Bruce Land