9 Results for "rtl-sdr"

Studio 68: a board for "retro experiments"
Project by Just4Fun
An FPGA-centric board to make "experiments" with old CPUs
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VHDL library for gate-level verification
Project by Yann Guidon / YGDES
Collection of ASIC cells and ProASIC3 "tiles" in VHDL so I can design and verify optimised code without the proprietary libraries
- 17
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TommiRouvali
Hacker
Finland

Mani19133
Hacker in Delhi
FPGA, VHDL Expert

Stanley Ng
Hacker in Bay Area, California
Engineer doing RTL design/verification in FPGAs and ASICs

Pradeep Purushothaman Vadakkodathu
Hacker
FPGA/SoC IP Designer. Worked in 5GNR UE development.

Tom
Hacker in Bay Area
I am a Computer Engineer that has a passion for Technology. My interests include Tea, Drones, 3D Printing, SDR, and FPGAs

Dan Johnson
Hacker in Crestwood, Kentucky
EDA, ASIC, FPGA, & Embedded Java engineer. Developing custom hardware and server platforms for 3D virtual worlds.

rcollins0618
Hacker in Utica, NY
never comfortable in complacency, always more to learn, never enough time, so much left to do,