One issue of the logic style I am using currently is that a D-Flipflop takes up no less than 15 units cells, 15 transistors, 30 resistors. This has a huge impact on design size and it would be great to do something about it.
Months ago, I had a nice discussion with Yann on the TTLer HaD chat and we were competing in trying to reduce the number of transistors in a latch as much as possible. One amazing contraption that came out of this is the design below, that would certainly deserve a more detailed treatment than I can offer here.
.SUBCKT NOT A Y
Q1 Y N001 VEE 0 RTL_NPN
R1 VCC A {RL}
R2 N001 A {RB}
.ENDS NOT
.SUBCKT TBUF E A Y
Q1 A N001 Y 0 RTL_NPN
R1 E N001 {RB}
R2 VCC A {RL}
R3 VCC E {RL}
.ENDS NOT
.SUBCKT NOTb A base Y
Q1 Y base VEE 0 RTL_NPN
R1 VCC A {RL}
R2 base A {RB}
.ENDS NOT
.SUBCKT DLATCH3Tn E D Qn
X1 E D N001 TBUF
X2 N002 N001 Qn NOTb
X3 Qn N002 NOT
.ENDS DLATCH
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I'm eager to see it working for real !!!
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It's working, i got the pcbs today.
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