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CPLD-flavored VGA Video card

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This project was created on 07/17/2014 and last updated 2 months ago.

Do you remember when 640x480 was a high resolution?

How about when *hundreds* of colors was a huge palette?

Does the pure awesomeness of dithering cause tears of nostalgia to well up in your assaulted-with-pixel-density eyes?

You've found the right project!

We've undertaken the ambitious challenge of fitting first generation display technologies - VGA and NTSC - on the smallest programmable logic device we think we can to create an embedded video card. Targeted for microcontrollers and headless Linux development boards and devices, VGAtonic promises to bring all the retro-video goodness you can shake a stick - or speak SPI - at.

The Executive Summary 

640x480 Video @ 8 bit color from a serial protocol that any Maker's parts can speak.

The Engineer's Report

As there are a number of interesting display-less dev boards and embedded linux products on the market nowadays (not to mention the 2 PogoPlugs and the Intel Galileo in my own parts bin), I set out to find a solution for getting reasonable video out of the world's collection of headless parts.  

VGAtonic is my effort to make said headless parts connect to the displays people already have lying around - monitors with VGA input, and TVs with their anachronistic NTSC RCA jacks.

Our goals are modest - 640x480 is still the fallback, worst case resolution for lots of applications - so we'll target VGA's original 640x480 spec.  Technically, the original VGA asked for just 4 bit color (read: 16 colors), but as an analog protocol we'll double the number of bits to 8 to get 256 colors.  NTSC is still undecided, but in our tests we've been producing 16 colors and 16 brightnesses: 256 colors the hard way.

For the brains, we'll be using a 4MBit ISSI IS61LV5128AL-10 with a Xilinx XC95144XL CPLD providing the brawn and the timing.  Our first reference design, a roughly 3"x3" PCB, was already released, and we decided to use a programmable oscillator (Linear Technology's LTC6903) and a microcontroller (Atmel's ATTiny 2313a) for board support and experimentation.  If we do another design, we'll try to tighten it up and actually target an interesting size.

Oh, and we're going to do it all with a BOM of roughly $23-$32 a board.

  • 1 × Xilinx XC95144XL 144 Macrocell CPLD
  • 1 × ISSI IS61LV5128AL-10 100 MHz 4MBit Static Ram
  • 1 × Linear Technology LTC6903 Programmable Oscillator
  • 1 × ON Semiconductor NCP1117ST33T3G 3.3V Low Dropout Voltage Regulator
  • 1 × Atmel Corporation ATTiny 2313a Microcontroller

Project logs
  • Working Example Code for the Intel Galileo (Arduino Mode)

    2 months ago • 0 comments

    I wanted to share some working code for the Intel Galileo board I've been showing in my videos.  With this update I'm declaring partial victory over this project, because now you can at least reproduce what I've shown in the videos.


    Motivation has waned a bit, but here's where I plan to go with this before I hit my 100% wish list:

    • User Mode in Linux (Done!  Just need to make a formatting/commenting effort and pull it off the Galileo)
    • Kernel Module / Framebuffer in Linux (This is the big one - in progress...)
    • NTSC Output activated (Not started)
    • Add features to CPLD firmware (Not started)

  • Breakout Boards for .5mm TQFP ICs

    2 months ago • 0 comments

    In response to a question in the comments by mylistgroups12, I wanted to show two of the breakout boards I acquired when starting this project.  I should note: I originally thought I might fit everything into a smaller CPLD (recall this post), which was in a 64 .5mm QFP size.  Still, I got a few breakouts which support the larger, 100 pin size - but even with the 64 pin broken out (I did 5 to practice with the smaller CPLD, but only added pins to one) it was tedious to wire Vcc/Vss.

    In the top right, of course, you can see VGAtonic - roughly 3" x 3", for scale.

    In the upper right is a breakout board I bought from Futurlec: (Currently: select 'Components' at top, then on the left 'Sockets', 'SMD Adapter').  It can only support an 100 pin chip, but it makes the pins easier to use/count.

    On the bottom is both sides of an adapter I bought on ebay from user e-sale2010.  I'd try searching 'QFP Adapter' - but this is nice because you can use anything from 32 - 100 pins in the .5mm pitch.  However, the pin count will be funky - I had to make a spreadsheet to convert the labeled pin number to the actual pin number on the CPLDs.

    Hope this helps!

  • CPLD Firmware Uploaded!

    2 months ago • 0 comments

    The moment that a few of you have been waiting for - a glimpse at my VHDL - is now here.  See the newest code in our git repo:

    You'll want to bring that into ISE Webpack and synthesize it.  I've been programming my CPLDs using a Bus Pirate; you can see that methodology here.

    Look in this directory for all of the demo code and design documents so far:

    The How to Use file details how this protocol works - it's very simple, I promise.

    I'll be back soon with firmware for the ATTiny onboard VGAtonic's reference design, along with the client code used in the Youtube demo.

View all 17 project logs


mylistgroups12 wrote 6 hours ago null point

Back again.
My computer died about a month ago. It's up an running again now. I now have a Xilinx DLC9-LP programmer. An I have loaded the Xilinx ISE.

I had only just started VHDL and then resorted to schematic entry when the computer died. This time I tried schematic entry again and found it just too frustrating with the ISE. When I went back to VHDL entry I discovered that I had completely forgotten the little that I had learnt lol. Still lots of bugs with ISE that I am working trough. It seems to be having trouble with windows long file names and keeps reporting that it can't find files and for some reason I have to reconfigure the programming software every time I want to program.

I am just at the stage of writing enough VHDL to flash a led on the board I have -
It's much like yours but has onboard regulation and a 50 MHz active oscillator. It based on the XC9572XL.

I looked up specs for the Z80 and the above chip and found that the Voh of the XC9572XL (3.3Volt chip) is above the Vih of the Z80 so that's a good sign lol.

I am going to plod along with this chip for now even if it lacks enough macros for the end project. I want to try different timings to see what works best.

I saw another project on HAD today -
Where the designer used a window within the full screen size to ease the timing demands. I am wondering if the pixel clock frequency is all that important with a modern monitor. Perhaps - as long as the active time and syncs are right then you could display a full screen with a different pixel clock. I will play with this and see. If it gives trouble then I will try different sync frequencies (different res for the monitor) and use a pixel clock that is an integer division of the expected frequency. ie monitor expects 25.175 but gets half that frequency. I will see what I can do from 50 MHz / x first as it's easy to get 50 MHz xtals but not so easy for 25.175 MHz and the like.

100 MHz would be good stating point if I can get away from anything derived from 25.175. Then I could divide to 20 MHz for the CPU and atMEGA1284, if is use one and 25 MHz for the pixel clock. I will also try clocking a 20 MHz Z80 at 25 MHz and 25.175 MHz. I know the atMEGA is easily overclocked as long as I use an active oscillator and not the internal crystal driver.

I am still waiting on fast SRAM (10nS) but I have some older 55nS SRAM to play with for now. I also have a color palate / RAMDAC to play with. Even if I don't have enough macros for a full interface I should still have enough to make some test patterns as proof of concept.

One thing that is obvious from your pic above is just how much board real estate is taken up by a LQFP 100 to 0.1" adapter. The adapter is half the size of the completed board. This is going to be a problem I have to face if I am going to use 0.1" pin spacings. I have considered PLCC sockets as they are 0.1" but also and extra expense both for the socket and the more expensive chip. Smaller 44 pin chips like a LQFP Z80 can easily sit on a LQFP to DIP adapter but 44 pins is probably not going to be enough IO for the CPLD.

Can I ask what CAD you using for your boards? I have to learn this to lol. I am just learning to make single sided boards by toner transfer. I don't want to take on double sided, they will have to come from a PCB manufacturer. I have used expressPCB and DIPTrace as they suit the manual manufacture process well but I expect they are not good for a PCB manufacturer. Any adapters will have to be double sided as there's just not enough room to do it on a single sides board for DIP adapters.

I know some of the XC95xx series come in a 84 pin PLCC, I am not sure if they come in a 84 pin LQFP but if they did then this may be a good compromise.

Anyway I will do some VHDL tutorials and have a look at your code.

Thanks, and keep up the good work!

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mylistgroups12 wrote 2 months ago null point

Can I ask which breakout board you are using in the picture - and where you bought it?

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PK wrote 2 months ago null point

Sure thing - I broke down both adapters I purchased and took another photo in the recent entry.

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Starhawk wrote 3 months ago null point

Just wanted to say: way cool project, and way cool results so far! Skull given, and project followed ;) Can't wait to see where this goes.

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PK wrote 3 months ago null point

Thank you! I've got some other stuff I just need to write up - documenting can sometimes be the greatest challenge, haha.

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Darren wrote 3 months ago null point

Why not use r2r resistor networks?

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PK wrote 3 months ago null point

For which schematic? I think you might be looking at my non-related AVR VGA post - I have the CPLD schematic with the output stages/ladders on page two.

For the AVR, they're actually implied - you'd have to look at the original on my site for my output stage, but it's all 510 ohm resistors as well ( I had a reel of like 200 of them - close enough to the 470 ohm I wanted in that).

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Darren wrote 3 months ago null point

The prepackaged ones like what bournes and others make.

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PK wrote 3 months ago null point

To be honest? A surplus of 510 ohm resistors in the parts drawer, and I didn't want to buy anything else. I had a reel of 510s for a computer project I worked on some time back - worked out well enough for this.

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Benchoff wrote 3 months ago null point

NTSC and VGA? Nice job.

You *are* entering this into the hackaday prize, right? All you need to do is tag the project with "TheHackadayPrize"

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PK wrote 3 months ago null point

That would have been a pretty bad oversight, eh? Thanks for the heads up!

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mylistgroups12 wrote 3 months ago null point

I am going to try something similar with a XC9572XL. Perhaps QVGA. I want it to work in with a Z80 and SRAM. I chose the lower pin count chip because it's easier to adapt to DIL.

I am new to HDL. I tried VHDL and I can do most things but I still lack experience. I tried Verilog and it's much easier to code with but I have trouble imagining how the code is implemented unlike VHDL. Now I have resorted to schematic entry.

It would be great to see your HDL as it will get me to understand it better.

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PK wrote 3 months ago null point

I learned Verilog first, but didn't touch any HDLs for a few years. When I came back to the game, I picked up VHDL and haven't looked back... and I write C++ at my day job (go figure). I prefer the strongly typed statements and the 'compiler' telling me what's sloppy - I think this project will be a lot more thought through than if I used verilog.

I definitely think you'll have a lot to reference with this project. Also, I think QVGA or even quarter-NTSC would be a reasonable target for a Z80. Have you thought about color depth yet? If you can accept 4 bit color instead of 8, you can do 160x120x4 = 76.8 kbits which is cheap and you can easily do in a DIP package... and everything will refresh 2x as fast as 8 bit.

I'll post a bit of VHDL soon - I want to record a demo working for video, as well as show my first draft on my SPI input scheme in the next few days.

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