Dan MaloneyOK, welcome to the Hack CHat. Had some trouble there for a bit, but we're good now. I'm Dan, I'll be moderating today. Let's welcome Tim Ansell to the chat to talk about SkyWater PDK
Hi! Testing :)
Oh right - and Michael Gielda, and hopefully Mohamed Kassem soon. Welcome!
Can Tim and Michael start us off with a little intro? And Mohamed now - gang's all here. Welcome!
Hello everyone!
Tim should do the honors! He's the reason we're here.
Hi Everyone! I was in the other channel!
So, we are here to chat about the "skywater-pdk" which was recently released by Google
It can be found at https://github.com/google/skywater-pdk
A PDK is an extremely important part required to create an integrated circuit like a CPU or similar.
Welcome Mohamed !
The skywater-pdk currently contains the low level information needed to create a manufacturable IC on SkyWater Foundry's SKY130 process -- which is roughly a 130nm process technology.
There is lots of documentation about the contents of the PDK found at https://skywater-pdk.readthedocs.io/en/latest/ -- I push a pretty big drop of new information yesterday that I have yet to announce.
The PDK contains things like the data needed for simulating the transistors and standard cells.
What would the 130-nm process represent historically? Like, how long ago was 130-nm cutting edge tech?
130nm is about a ~20 year old technology.
2003'ish
I believe "high performance" CPUs created with 130nm technology were just hitting the market in 1999
So it's still 21st century tech! that used to mean it's new ;)
I actually have a "living document" at https://j.mp/si130nm which is suppose to include a bunch of information around what is possible with 130nm
THere were still a lot of interesting chips 20 years ago though, right>
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130 less leaky ... a good thing
oh wow
I like inspirational information, having no frame of reference for what can be done with the given area
The Intel PentiumB 4 Processor, Intel Itanium2 Processor and IBM PowerPC 970 all done on 130nm process nodes
These days 130nm is generally used for microcontrollers
130nm is a sweet spot for prices, speed, power and a mature process has much fewer unknowns
How's the process for analog / power / HV?
As @Yann Guidon / YGDES points out 130nm is just before you start seeing a lot of more complex physics needing to be involved in modeling the process
I think we should all look at the fact that this is the first manufacturable open source PDK. There are "many" applications that benefit from the quality of components and the price/cost
I should also mentioned I'm not an ASIC / IC designer, I'm a software engineer at heart. @Mohamed Kassem is the person who can answer more technical questions around that.
@Patrick Van Oosterwijck it has a good array of devices to support unto 20V (need to confirm if there is more)
So the process limit is more a practical limit that something imposed arbitrarily for like IP reasons or something?
I *believe* 130nm is a node that a lot of analog designers like because of the physics.
Indeed it is not the last, but I think that for many small companies and universities it is a valuable approach for testing ideas, especially when designs are non-FPGA friendly
For sure. Rolling your own IC's is something i hadn't even considered until now. If you have IC's made are they packaged?
@Dan Maloney -- I'm sure there will be more advanced process nodes in the future, but you have to start somewhere.
the wold is turning around
so i could design a multicore 8- or 16-bit processor to play with using this tech?
right and if I remember history right after p4 they went to mulitthreaded because frequency scaling and heat density
it is not about the process .. it is about what you can do with it
does the process size have a relationship to the clock speed of a processor? or is it a lot more complex than that?
as far as I know analog or mixed-focused companies are still using 130nm for some stuff today
Are there any digital synthesis / place and route tools availble for it?
deep nm technologies are optimized for hi performance/low power/low leakage
What you *can* do with the process and what it makes economic sense to do with a process is somewhat different
the part that is less clear to me is about the packing and support
*packaging
YoSys+OpenLANE+PDK mean design tools are free. This cuts a huge startup cost for ASIC fab out of the equation. I understand there will be a shuttle in November that is free for open source. Long term, what do you think the cost range will be for tinkerers and small startups looking to make products with skywater?
If you want more background on the PDK and how it fits in connection with the whole IC design space, I tried to explain it further in my talk at
openlane? intersting...I've been trying to useqrouter et similia
Which is part of the FOSSi Dial-Up talk series
I haven't looked at the PDK yet, but can custom stdcell libraries that pass DRC can be created and then implemented into synth, enabling full-custom design? (My research is in multi-threshold CMOS-based asynchronous architectures that require their own stdcell library.)
just opened lane.io, it only shows a generic screen indicating that the domain is registered
efabless/openlane
OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization. The flow performs full ASIC implementation steps from RTL all the way down to GDSII - this capability will be released in the coming weeks with completed SoC design examples that have been sent to SkyWater for fabricaiton.
thanks @Michael Gielda !
@brettspark Yes! In fact I pushed (but again have not advertised) the spice models for the low level transistors yesterday -- https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_pr
any data on 130 run at cryo temps?
Or between 100C and 200C...
@brettspark James Stine from OSU will be giving a talk about designing standard cells for the SKY130 process at the next FOSSi DialUp -- https://fossi-foundation.org/dial-up/ --
Date: Tuesday, September 22, 2020 - Time: 16:00 GMT
His team is also working on doing a recharacterization of the existing foundry provided standard cells too
I want to build a fanless computer with one of the open Power cores IBM just released and it would make the design a lot easier to use boiling water at near atmospheric pressure as the coolant
@Tim Ansell Thanks for the info. Signing up!
well, that's the kind of thing we want to enable, right? for some people to come and say "well we tried running this in cryo temps just because it's open and it was so much easier to work with than closed stuff" -- en
-- enabling niche applications is one of the benefits of open source
James Stine is pretty active on the PDK slack (which again can be joined via https://join.skywater.tools), so you can chat with him directly too.
One other "dirty" question is about DRC - which was listed as "TODO" the last time I saw - what are the plans for acceptable DRC verification?
where people normally might not have done things before just because of the entry cost, licenses, NDAs etc. also ability to disseminate things more easily is very valuable for researchers. when it's an open PDK / process, you can just throw stuff at people on GitHub, and it's end to end reproducible.
my research includes also PUF design, for which aging effect on ICs is an important aspect: are aging model included within the PDK?
@Art Scott / @Troy Benjegerdes -- There has been a lot of interest in bringing up a fully open source "technology CAD" solution for the SKY130 process node which could be used to get that data.
@Art Scott @Troy Benjegerdes It is not about "can it work" at extreme temps, it is about is it modeled? the answer for me is to just do it
@Michael Gielda you sound like you have a business marketing aspect to this ;)
Hello everyone
yeah, for @Mohamed Kassem the answer is very often to just do it :) he is a doer
I'm looking at DeepSpec design flow ... a lot of software ... is that a future trend?
however to really 'just do that', I need to know what it costs to run my own wafer.. Do we have any public docs on that or do I need to go talk to Skywater under NDA ;)
Technology CAD is all about simulating the physical processes and results which allows you to ask questions like that.
@Troy Benjegerdes that's my job actually. The nice part tho is that we practically only work with open source, so it's really nice to do marketing around.
Can we request samples / purchase demo parts that were made with this specific process - that might contain some simple test structures or logic that we could see?
@Troy Benjegerdes I can get you a rough order of mag based on other available 130nm .. for SKY130 is is being refined
@Troy Benjegerdes -- Foundries have incentives to enable people to create new technologies and stuff that their customers can use.
is there any attempt to build an arm core on this process?
I do believe Arm cores have been built using this process
sky130 or 130nm?
@Michael Gielda is on the RISC-V marketing committee IIRC :-)
@Kelsey Rosenthal there is no reason not to .... as long as you have a license :-)
@Troy Benjegerdes With creation of open source IP that any of their customer can freely use there is a clear reason they might want to help you out with silicon access.
both RiscV and OpenPower consortiums seem to understand the business value of open source. It's not so clear about Nvidia/Arm...
ah, you mean SKY130. I don't think there are any attempts yet
The analog section on readthedocs is pretty much all TODO at the moment. Any other place to get info?
Do you have any how to guides for using the Skywater PDK with LayoutEditor?
but who knows, it's open source :P
right the concern question comes from a place of adoption with arm being pretty accessible having it on the process already makes it easier to play with
@Kelsey Rosenthal There was a doc shared further up the chat. Looks like ARM Mx wer built using it.
@Troy Benjegerdes Much easier to also justify the engagement if you *already* have working in simulation device.
ah lovely
FYI, I'll be posting a transcript right after the chat if you need to refer back to any links, etc.
SkyWater Technology has other customers, such as Cypress who did the PSoC series
@Tim Ansell so along those lines, is there any linux-capable core that's been run through to GDS with the open PDK
The Cypress cy8c4245axi - PSoC 4200 was 2120 x 3210 μm (6.80 mm2) and had a Cortex-M0 CPU at up to 48 MHz
@Troy Benjegerdes that's where we want to get to, but certainly not where we are right now
I can handwave about the memory controller for a little while, but I'll need a DDR3/4 controller at some point
@Troy Benjegerdes not sure why "you" can't do that
we are in MCU world currently
You can apparently even seem SEM images of the part at https://siliconpr0n.org/archive/doku.php?id=azonenberg:cypress:cy8c4245axi
@Mohamed Kassem I certainly *can* do that, but where do I apply for a grant from RiscV or Openpower foundations to cover my opportunity cost ...
My business model of AGPLv3 licensed hardware doesn't work with the Google 'free' shuttle...
@Troy Benjegerdes The big problem with Linux capable core is going to be the lack of IO to external memory and the size of any internal caches -- 130nm doesn't get you a lot kilobytes of SRAM per mm
Anyone looking at circuits that can defend against any kind of hardware Trojans?
@Tim Ansell get me a quote for what it costs to make my own wafer and I'll have that problem solved
TO ALL: this process has been used in many many many products over the years and it has a long life time. Look at it this way, if the Pent. Processor was built using it ay 1.5GHz + clock .. why can't we squeeze this first
Things like QSPI RAM, HyperRAM and ReducePinCount-DDR could all potentially solve the external memory issue
I want to build a single wafer with cores + ram
I should have plenty of area to boot linux, even if it's just SRAM
@Troy Benjegerdes you can do this this afternoon :-)
@Mohamed Kassem Too true! Can do lots with 130 and VALUE designs.
ram is generally done in a very different process than compute, at best joined on package
@Mohamed Kassem can you point me to a github with a linux-capable core I can synthesize to a GDS file yet ;)
@Troy Benjegerdes Cost is dependent on the number of wafers you commit to over what timeframe. A typical "lot" of wafers at 130nm is 300mm diameter at 25 whole wafers.
@Art Scott we should think .. what pppa are we looking for ...
@Troy Benjegerdes BlackParrot, VexRISCV and Rocket are all candidates for that
https://github.com/black-parrot/black-parrot
black-parrot/black-parrot
BlackParrot aims to be the default open-source, Linux-capable, cache-coherent, RV64GC multicore used by the world. Although originally developed by the University of Washington and Boston University, BlackParrot strives to be community-driven and infrastructure agnostic, a core which is Pareto optimal in terms of power, performance, area and complexity.
@Kelsey Rosenthal https://spectrum.ieee.org/nanoclast/semiconductors/processors/the-foundry-at-the-heart-of-darpas-plan-to-let-old-fabs-beat-new-ones looks like a good candidate for memory...
https://github.com/SpinalHDL/VexRiscv
SpinalHDL/VexRiscv
This repository hosts a RISC-V implementation written in SpinalHDL.
https://bar.eecs.berkeley.edu/projects/rocket_chip.html
Rocket Chip Generator
Rocket Chip is Berkeley's RISC-V based SOC generator. The open-source release is capable of generating a multi-core system with Rocket scalar cores, Z-Scale control processors, and a coherent memory system. Rocket Chip is BAR's paramaterizable chip generator, and serves as the basis for all the RISC-V implementations that we produce.
Does anyone know the cost per mm2 on the MPW runs ?
I'm quite familiar with https://github.com/tmagik/rocket-chip
@Troy Benjegerdes - So, why haven't you created GDS yet? :-P
Was there a video i missed or something?
business constraints.. I need to know what it costs me to make an entire wafer and do some projections on how many runs I have to do.
Google does not appear to want to fab anything with a license that protects my business model :P
@keyes118 we do but we want to reduce it even more - right now other foundries charge ... low volume .. ~$1100~$1500
Otherwise I'm developing free IP and donating it to Google without getting paid
@Key
@keyes118 aiming for less with SKY130 .. outside the Gogle free shuttle program
@keyes118 and yes I am deliberately vague :-) sorry
@Tim Ansell and I'm being deliberately vague on why I haven't done a GDS yet for much the same reasons @Mohamed Kassem is ;)
@Mohamed Kassem Excellent!
@Troy Benjegerdes I'm personally not particularly interested in Linux capable cores on SKY130 but I'm excited to see other people try.
Tim Ansell - Kick Off
Mohamed Shalan - OpenLANE Design Flow
Mohamed Kassem - First SoCs designed on the sky130 in the open
from my experience the higher cost to amortize is not the wafers but the masks, and info on how much those are looking at?
@Mohamed Kassem are there any more details on the caravel SoC source?
the mask cost is what's going to kill me on building linux-capable SoC propotypes
@Kelsey Rosenthal the numbers above are per mm2 ... mask cost factored in - assuming a shared shuttle
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