Open Source Chip Design Hack Chat

Join us in a discussion with SiFive about custom silicon and RISC-V

Friday, April 14, 2017 12:00 pm PDT - Friday, April 14, 2017 12:30 pm PDT Local time zone:
Hack Chat
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Come hang out for 30 or so minutes and talk to Jack Kang, VP of Product and Business Development at SiFive. Join this chat to learn about RISC-V, the free and open Instruction Set. Ask questions about what it means to have open-source chips, and how SiFive plans to help everybody—from the smallest company, inventor, and maker, get access to custom silicon.

About @Jack Kang :: Jack started his career as a frontend design engineer, with a focus on CPU architecture and design. Jack received his BS degree in Electrical Engineering and Computer Science from UC Berkeley.

About SiFive :: SiFive was founded by the creators of the free and open RISC-V architecture as a reaction to the end of conventional transistor scaling and escalating chip design costs. SiFive believes that by enabling the power of open-source hardware design, custom silicon is available to everyone, enabling a whole new range of applications.

We're meeting in the #Hack Chat on April 14th, noon PDT.

Here's the list for discussion and questions, add yours to the sheet!

  • Open Source Chip Design Hack Chat Transcript

    Shulie Tornel04/14/2017 at 19:57 0 comments

    Jack Kang Sure, hi everybody! My name is Jack and I am VP of Product and Business Development at SiFive. before SiFive, I started my career as a front end chip designer, working on bus controllers, memory controllers, and CPUs. then moved into product marketing/management/BD etc at large chip companies, both Marvell and NVIDIA. SiFive was founded by the inventors of RISC-V, and our mission is to make custom silicon available to all

    Jack Kang Our chips are all based on the free and open RISC-V ISA, and we launched our first chip, the FE310 last November, which itself is also open sourced

    Sophi Kravitz Can you walk us through the "getting a chip made" process

    Jack Kang it's a very long and expensive process that's getting longer and more expensive! at least, that's the direction it's been heading at most chip companies. back in the old days, when Moore's law was humming along, everybody would just rush to go to the next node ASAP--because things would just be cheaper and faster. so the methodology of many of the traditional chip companies have been built around that idea. at the simplest level, you have a front end team that's focused on the RTL/digital portion of the design, which would then pass it off to the backend team, which would work on the physical design/synthesis/etc., then pass it along to foundries to actually manufacture. the front end team and back end teams work independently, and the number of folks required has grown as these chips have grown in complexity. so the entire design cycle these days from defining a chip, going through the front end + back end plus manufacturing is easily 18+ months for the advanced process nodes. sorry, your question was pretty broad so not sure where you'd like me to focus down a bit more on :)

    Sophi Kravitz what is an advanced process node? (that was a good explanation thanks!)

    Jack Kang the nodes refer to the size of the in recent years we've gone from 40nm process to 28nm to 16nm (or 14nm)

    Jack Kang there was a big jump once we went to 16nm and below because we now use FINFET transistors

    Jack Kang some people also call those 3D transistors

    Sophi Kravitz ooooo what are those?

    Jack Kang so these days an advanced node is probably a finfet node of lower (16nm/14nm, 10nm, 7nm)

    Piotr Esden-Tempski Which node is SiFive concentrating on. I assume you are not going all the way to the most modern nodes due to cost?

    Jack Kang the transistor is basically a switch, with a gate in the middle. We used to lay these down flat. with a finfet, the gate stands up (kind of like a shark fin, which is why it's called FINFET) they flip it. SiFive is focused on two nodes at the moment: 180nm and 28n. the 180nm is for our microcontroller/IOT type low cost platform. 28nm is still a very advanced node that allows for high performance CPU, PCIe Gen3, DDR4 @ 2400 MT/s.

    Lars R. With more and more Opensource tools becoming available, are you going to enter into Opensource FPGA development? You could even add the Risc-V as a hard macro.

    Jack Kang I think and opensource FPGA and FPGA tool flow would be great for the ecosystem as whole!! but for now, we have to be content with people using open source RTL and mapping it down to the FPGAs. a hard macro RISC-V inside a FPGA...would be a great accomplishment for RISC-V.

    Karim Yaghmour What tools do you use to synthesize your chips? And do you do this in-house or do you outsource that?

    Jack Kang i guess i'll just say there are multiple FPGA companies as part of the RISC-V foundation and leave it at that ;)

    Matt D. I'm curious, have you been using some of the formal verification tools at SiFive, e.g., Yosys-SMTBMC?

    Jack Kang We use commercial tools from the EDA vendors, and we do that inside of SiFive. Formal verification is a big part of what we do. A major area of focus for us is to be able to customize silicon for customers. when you customize, you want to be able to verify that the customizations don't introduce any bugs or unforseen side effect. leveraging formal...

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