At Synopsys' annual user conference in Silicon Valley, industry experts who participated in a panel said that FinFETs have potential, but they also have risks, and the technology is the best time to do so. not yet reached.

The technical director from the wafer foundry Globalfoundries pointed out that this 3D transistor architecture will bring performance improvements in the 14nm process node, and the power consumption will also be reduced by 60% compared with the current 28nm process; however, other participating experts pointed out that, This transistor architecture exacerbates some old design problems and brings new challenges due to the increased capacitance.

Anil Jain, vice president of IC engineering at processor designer Cavium Networks, said that compared with the current 28nm process, FinFET gate capacitance per micron (micron) has increased by 66%, returning to the previous 130nm process. The level of node planar transistor architecture; he added that capacitors will limit the performance improvement and dynamic power scaling of high-end chips.

"We have these beautiful (3D) transistors, but we can't get them to go very far," Jain points out. "The dynamic power can get out of hand." 

Jain called on EDA suppliers to provide design tools that are better at controlling switching power and isolating electromagneTIc faults, "FinFET is not an easy technology to switch, and we will have to pay for it until the day it succeeds, so please don't. Let's go bankrupt."

Michael Campbell, vice president of engineering at Qualcomm's chip design division, said that the FinFET architectures of different foundries are "similar, but not identical. You can only etch in a certain direction, and the etching tools are shared-- Those are the reasons for their similarities -- but each foundry actually uses different techniques for spaTIal walls and diffusion."

Campbell pointed out that the irregular tapered walls seen in Intel's 22nm FinFET pictures could impact the defect model of planar transistors, requiring new testing techniques and a very close partners relationship in order to complete a proper testable design.

And Campbell said Synopsys' Yield Explorer is a good tool in the EDA space, but it's still locked down to planar transistor architectures -- the company needs to introduce tools for 3D transistor architectures. He pointed out that neither Synopsys nor other EDA vendors' design tools have a serious lack of solutions to compress simple ATE graphics for backward-finding defects.